From patchwork Wed Mar 2 07:34:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 63369 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2242264lbc; Tue, 1 Mar 2016 23:37:33 -0800 (PST) X-Received: by 10.31.130.6 with SMTP id e6mr15690770vkd.49.1456904246451; Tue, 01 Mar 2016 23:37:26 -0800 (PST) Return-Path: Received: from lists.xen.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p13si498455vkp.155.2016.03.01.23.37.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Mar 2016 23:37:26 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KK-0004oe-Sb; Wed, 02 Mar 2016 07:36:08 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KJ-0004mx-36 for xen-devel@lists.xen.org; Wed, 02 Mar 2016 07:36:07 +0000 Received: from [85.158.139.211] by server-7.bemta-5.messagelabs.com id 46/32-13547-6E796D65; Wed, 02 Mar 2016 07:36:06 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-6.tower-206.messagelabs.com!1456904161!25859171!1 X-Originating-IP: [119.145.14.66] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NiA9PiA4NTI3\n X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 51661 invoked from network); 2 Mar 2016 07:36:04 -0000 Received: from szxga03-in.huawei.com (HELO szxga03-in.huawei.com) (119.145.14.66) by server-6.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 2 Mar 2016 07:36:04 -0000 Received: from 172.24.1.47 (EHLO SZXEML424-HUB.china.huawei.com) ([172.24.1.47]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BXB04001; Wed, 02 Mar 2016 15:35:39 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML424-HUB.china.huawei.com (10.82.67.153) with Microsoft SMTP Server id 14.3.235.1; Wed, 2 Mar 2016 15:35:18 +0800 From: Shannon Zhao To: Date: Wed, 2 Mar 2016 15:34:35 +0800 Message-ID: <1456904083-13168-10-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> References: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.56D697CC.00A6, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 514df7942f659d94531b5e3a49b4c6ed Cc: zhaoshenglong@huawei.com, stefano.stabellini@citrix.com, ian.campbell@citrix.com, shannon.zhao@linaro.org Subject: [Xen-devel] [PATCH v8 09/17] arm/irq: Drop the DT prefix of the irq line type X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Make these types generic to DT and ACPI. So they are can be used in ACPI codes. Signed-off-by: Shannon Zhao Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain_build.c | 10 ++++----- xen/arch/arm/gic-v2.c | 10 ++++----- xen/arch/arm/gic-v3.c | 8 +++---- xen/arch/arm/gic.c | 4 ++-- xen/arch/arm/irq.c | 8 +++---- xen/arch/arm/time.c | 2 +- xen/include/xen/device_tree.h | 50 +++++++++++++++++++++---------------------- 7 files changed, 46 insertions(+), 46 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 0f0f53e..83676e4 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -650,7 +650,7 @@ static int make_hypervisor_node(const struct kernel_info *kinfo, * Placeholder for the event channel interrupt. The values will be * replaced later. */ - set_interrupt_ppi(intr, ~0, 0xf, DT_IRQ_TYPE_INVALID); + set_interrupt_ppi(intr, ~0, 0xf, IRQ_TYPE_INVALID); res = fdt_property_interrupts(fdt, &intr, 1); if ( res ) return res; @@ -923,15 +923,15 @@ static int make_timer_node(const struct domain *d, void *fdt, irq = timer_get_irq(TIMER_PHYS_SECURE_PPI); DPRINT(" Secure interrupt %u\n", irq); - set_interrupt_ppi(intrs[0], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); + set_interrupt_ppi(intrs[0], irq, 0xf, IRQ_TYPE_LEVEL_LOW); irq = timer_get_irq(TIMER_PHYS_NONSECURE_PPI); DPRINT(" Non secure interrupt %u\n", irq); - set_interrupt_ppi(intrs[1], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); + set_interrupt_ppi(intrs[1], irq, 0xf, IRQ_TYPE_LEVEL_LOW); irq = timer_get_irq(TIMER_VIRT_PPI); DPRINT(" Virt interrupt %u\n", irq); - set_interrupt_ppi(intrs[2], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); + set_interrupt_ppi(intrs[2], irq, 0xf, IRQ_TYPE_LEVEL_LOW); res = fdt_property_interrupts(fdt, intrs, 3); if ( res ) @@ -1463,7 +1463,7 @@ static void evtchn_fixup(struct domain *d, struct kernel_info *kinfo) * TODO: Handle properly the cpumask */ set_interrupt_ppi(intr, d->arch.evtchn_irq, 0xf, - DT_IRQ_TYPE_LEVEL_LOW); + IRQ_TYPE_LEVEL_LOW); res = fdt_setprop_inplace(kinfo->fdt, node, "interrupts", &intr, sizeof(intr)); if ( res ) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 3fb5823..668b863 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -209,16 +209,16 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, unsigned int irq = desc->irq; unsigned int type = desc->arch.type; - ASSERT(type != DT_IRQ_TYPE_INVALID); + ASSERT(type != IRQ_TYPE_INVALID); ASSERT(spin_is_locked(&desc->lock)); spin_lock(&gicv2.lock); /* Set edge / level */ cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4); edgebit = 2u << (2 * (irq % 16)); - if ( type & DT_IRQ_TYPE_LEVEL_MASK ) + if ( type & IRQ_TYPE_LEVEL_MASK ) cfg &= ~edgebit; - else if ( type & DT_IRQ_TYPE_EDGE_BOTH ) + else if ( type & IRQ_TYPE_EDGE_BOTH ) cfg |= edgebit; writel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4); @@ -232,8 +232,8 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, cfg & edgebit ? "Edge" : "Level", actual & edgebit ? "Edge" : "Level"); desc->arch.type = actual & edgebit ? - DT_IRQ_TYPE_EDGE_RISING : - DT_IRQ_TYPE_LEVEL_HIGH; + IRQ_TYPE_EDGE_RISING : + IRQ_TYPE_LEVEL_HIGH; } /* Set target CPU mask (RAZ/WI on uniprocessor) */ diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index fa61231..a42577b 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -491,9 +491,9 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, cfg = readl_relaxed(base); edgebit = 2u << (2 * (irq % 16)); - if ( type & DT_IRQ_TYPE_LEVEL_MASK ) + if ( type & IRQ_TYPE_LEVEL_MASK ) cfg &= ~edgebit; - else if ( type & DT_IRQ_TYPE_EDGE_BOTH ) + else if ( type & IRQ_TYPE_EDGE_BOTH ) cfg |= edgebit; writel_relaxed(cfg, base); @@ -508,8 +508,8 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, cfg & edgebit ? "Edge" : "Level", actual & edgebit ? "Edge" : "Level"); desc->arch.type = actual & edgebit ? - DT_IRQ_TYPE_EDGE_RISING : - DT_IRQ_TYPE_LEVEL_HIGH; + IRQ_TYPE_EDGE_RISING : + IRQ_TYPE_LEVEL_HIGH; } affinity = gicv3_mpidr_to_affinity(cpu); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 0b3f634..43e6fa2 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -98,7 +98,7 @@ void gic_restore_state(struct vcpu *v) * needs to be called with a valid cpu_mask, ie each cpu in the mask has * already called gic_cpu_init * - desc.lock must be held - * - arch.type must be valid (i.e != DT_IRQ_TYPE_INVALID) + * - arch.type must be valid (i.e != IRQ_TYPE_INVALID) */ static void gic_set_irq_properties(struct irq_desc *desc, const cpumask_t *cpu_mask, @@ -223,7 +223,7 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, *out_hwirq += 16; if ( out_type ) - *out_type = intspec[2] & DT_IRQ_TYPE_SENSE_MASK; + *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; return 0; } diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index d409abb..0ff5cbc 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -66,7 +66,7 @@ irq_desc_t *__irq_to_desc(int irq) int __init arch_init_one_irq_desc(struct irq_desc *desc) { - desc->arch.type = DT_IRQ_TYPE_INVALID; + desc->arch.type = IRQ_TYPE_INVALID; return 0; } @@ -117,7 +117,7 @@ void __init init_IRQ(void) spin_lock(&local_irqs_type_lock); for ( irq = 0; irq < NR_LOCAL_IRQS; irq++ ) - local_irqs_type[irq] = DT_IRQ_TYPE_INVALID; + local_irqs_type[irq] = IRQ_TYPE_INVALID; spin_unlock(&local_irqs_type_lock); BUG_ON(init_local_irq_data() < 0); @@ -449,7 +449,7 @@ int route_irq_to_guest(struct domain *d, unsigned int virq, spin_lock_irqsave(&desc->lock, flags); - if ( desc->arch.type == DT_IRQ_TYPE_INVALID ) + if ( desc->arch.type == IRQ_TYPE_INVALID ) { printk(XENLOG_G_ERR "IRQ %u has not been configured\n", irq); retval = -EIO; @@ -591,7 +591,7 @@ void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) static bool_t irq_validate_new_type(unsigned int curr, unsigned new) { - return (curr == DT_IRQ_TYPE_INVALID || curr == new ); + return (curr == IRQ_TYPE_INVALID || curr == new ); } int irq_set_spi_type(unsigned int spi, unsigned int type) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 40f4758..73a1a3e 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -222,7 +222,7 @@ static void check_timer_irq_cfg(unsigned int irq, const char *which) * The interrupt controller driver will update desc->arch.type with * the actual type which ended up configured in the hardware. */ - if ( desc->arch.type & DT_IRQ_TYPE_LEVEL_MASK ) + if ( desc->arch.type & IRQ_TYPE_LEVEL_MASK ) return; printk(XENLOG_WARNING diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 5c03f40..cf31e50 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -105,33 +105,33 @@ struct dt_phandle_args { /** * IRQ line type. * - * DT_IRQ_TYPE_NONE - default, unspecified type - * DT_IRQ_TYPE_EDGE_RISING - rising edge triggered - * DT_IRQ_TYPE_EDGE_FALLING - falling edge triggered - * DT_IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered - * DT_IRQ_TYPE_LEVEL_HIGH - high level triggered - * DT_IRQ_TYPE_LEVEL_LOW - low level triggered - * DT_IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits - * DT_IRQ_TYPE_SENSE_MASK - Mask for all the above bits - * DT_IRQ_TYPE_INVALID - Use to initialize the type - */ -#define DT_IRQ_TYPE_NONE 0x00000000 -#define DT_IRQ_TYPE_EDGE_RISING 0x00000001 -#define DT_IRQ_TYPE_EDGE_FALLING 0x00000002 -#define DT_IRQ_TYPE_EDGE_BOTH \ - (DT_IRQ_TYPE_EDGE_FALLING | DT_IRQ_TYPE_EDGE_RISING) -#define DT_IRQ_TYPE_LEVEL_HIGH 0x00000004 -#define DT_IRQ_TYPE_LEVEL_LOW 0x00000008 -#define DT_IRQ_TYPE_LEVEL_MASK \ - (DT_IRQ_TYPE_LEVEL_LOW | DT_IRQ_TYPE_LEVEL_HIGH) -#define DT_IRQ_TYPE_SENSE_MASK 0x0000000f - -#define DT_IRQ_TYPE_INVALID 0x00000010 + * IRQ_TYPE_NONE - default, unspecified type + * IRQ_TYPE_EDGE_RISING - rising edge triggered + * IRQ_TYPE_EDGE_FALLING - falling edge triggered + * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered + * IRQ_TYPE_LEVEL_HIGH - high level triggered + * IRQ_TYPE_LEVEL_LOW - low level triggered + * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits + * IRQ_TYPE_SENSE_MASK - Mask for all the above bits + * IRQ_TYPE_INVALID - Use to initialize the type + */ +#define IRQ_TYPE_NONE 0x00000000 +#define IRQ_TYPE_EDGE_RISING 0x00000001 +#define IRQ_TYPE_EDGE_FALLING 0x00000002 +#define IRQ_TYPE_EDGE_BOTH \ + (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 +#define IRQ_TYPE_LEVEL_LOW 0x00000008 +#define IRQ_TYPE_LEVEL_MASK \ + (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH) +#define IRQ_TYPE_SENSE_MASK 0x0000000f + +#define IRQ_TYPE_INVALID 0x00000010 /** * dt_irq - describe an IRQ in the device tree * @irq: IRQ number - * @type: IRQ type (see DT_IRQ_TYPE_*) + * @type: IRQ type (see IRQ_TYPE_*) * * This structure is returned when an interrupt is mapped. */ @@ -140,12 +140,12 @@ struct dt_irq { unsigned int type; }; -/* If type == DT_IRQ_TYPE_NONE, assume we use level triggered */ +/* If type == IRQ_TYPE_NONE, assume we use level triggered */ static inline bool_t dt_irq_is_level_triggered(const struct dt_irq *irq) { unsigned int type = irq->type; - return (type & DT_IRQ_TYPE_LEVEL_MASK) || (type == DT_IRQ_TYPE_NONE); + return (type & IRQ_TYPE_LEVEL_MASK) || (type == IRQ_TYPE_NONE); } /**