From patchwork Fri Feb 26 06:22:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 62947 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp547594lbc; Thu, 25 Feb 2016 22:25:33 -0800 (PST) X-Received: by 10.140.241.5 with SMTP id m5mr47341736qhc.98.1456467933352; Thu, 25 Feb 2016 22:25:33 -0800 (PST) Return-Path: Received: from lists.xen.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n14si11870980qkl.12.2016.02.25.22.25.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Feb 2016 22:25:33 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aZBpa-0006h1-BY; Fri, 26 Feb 2016 06:24:50 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aZBpY-0006dT-Rn for xen-devel@lists.xen.org; Fri, 26 Feb 2016 06:24:48 +0000 Received: from [193.109.254.147] by server-1.bemta-14.messagelabs.com id 40/03-02901-0BFEFC65; Fri, 26 Feb 2016 06:24:48 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1456467882!18257576!1 X-Originating-IP: [58.251.152.64] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 13774 invoked from network); 26 Feb 2016 06:24:46 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (58.251.152.64) by server-11.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 26 Feb 2016 06:24:46 -0000 Received: from 172.24.1.47 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.47]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DFG21624; Fri, 26 Feb 2016 14:24:13 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Fri, 26 Feb 2016 14:24:01 +0800 From: Shannon Zhao To: Date: Fri, 26 Feb 2016 14:22:55 +0800 Message-ID: <1456467780-8476-18-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1456467780-8476-1-git-send-email-zhaoshenglong@huawei.com> References: <1456467780-8476-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.56CFEF8E.003F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: da19b2b0956ef3448e6740a00fea38a1 Cc: peter.huangpeng@huawei.com, stefano.stabellini@citrix.com, ian.campbell@citrix.com, shannon.zhao@linaro.org Subject: [Xen-devel] [PATCH v5 17/22] arm/acpi: Parse GTDT to initialize timer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Parse GTDT (Generic Timer Descriptor Table) to initialize timer. Using the information presented by GTDT to initialize the arch timer (not memory-mapped). Signed-off-by: Parth Dixit Signed-off-by: Shannon Zhao Reviewed-by: Stefano Stabellini --- V5: Move READ_SYSREG32(CNTFRQ_EL0) / 1000 to common place and simplify #else case V4: Factor dt parts --- xen/arch/arm/time.c | 86 +++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 70 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 73a1a3e..5f8f974 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -65,8 +66,51 @@ unsigned int timer_get_irq(enum timer_ppi ppi) static __initdata struct dt_device_node *timer; +#ifdef CONFIG_ACPI +static u32 __init acpi_get_timer_irq_type(u32 flags) +{ + return (flags & ACPI_GTDT_INTERRUPT_MODE) ? IRQ_TYPE_EDGE_BOTH + : IRQ_TYPE_LEVEL_MASK; +} + +/* Initialize per-processor generic timer */ +static int __init arch_timer_acpi_init(struct acpi_table_header *header) +{ + u32 irq_type; + struct acpi_table_gtdt *gtdt; + + gtdt = container_of(header, struct acpi_table_gtdt, header); + + /* Initialize all the generic timer IRQ variable from GTDT table */ + irq_type = acpi_get_timer_irq_type(gtdt->non_secure_el1_flags); + irq_set_type(gtdt->non_secure_el1_interrupt, irq_type); + timer_irq[TIMER_PHYS_NONSECURE_PPI] = gtdt->non_secure_el1_interrupt; + + irq_type = acpi_get_timer_irq_type(gtdt->secure_el1_flags); + irq_set_type(gtdt->secure_el1_interrupt, irq_type); + timer_irq[TIMER_PHYS_SECURE_PPI] = gtdt->secure_el1_interrupt; + + irq_type = acpi_get_timer_irq_type(gtdt->virtual_timer_flags); + irq_set_type(gtdt->virtual_timer_interrupt, irq_type); + timer_irq[TIMER_VIRT_PPI] = gtdt->virtual_timer_interrupt; + + irq_type = acpi_get_timer_irq_type(gtdt->non_secure_el2_flags); + irq_set_type(gtdt->non_secure_el2_interrupt, irq_type); + timer_irq[TIMER_HYP_PPI] = gtdt->non_secure_el2_interrupt; + + return 0; +} + +static void __init preinit_acpi_xen_time(void) +{ + acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init); +} +#else +static void __init preinit_acpi_xen_time(void) { } +#endif + /* Set up the timer on the boot CPU (early init function) */ -void __init preinit_xen_time(void) +static void __init preinit_dt_xen_time(void) { static const struct dt_device_match timer_ids[] __initconst = { @@ -75,6 +119,7 @@ void __init preinit_xen_time(void) }; int res; u32 rate; + unsigned int i; timer = dt_find_matching_node(NULL, timer_ids); if ( !timer ) @@ -82,27 +127,12 @@ void __init preinit_xen_time(void) dt_device_set_used_by(timer, DOMID_XEN); - res = platform_init_time(); - if ( res ) - panic("Timer: Cannot initialize platform timer"); - res = dt_property_read_u32(timer, "clock-frequency", &rate); if ( res ) { cpu_khz = rate / 1000; timer_dt_clock_frequency = rate; } - else - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; - - boot_count = READ_SYSREG64(CNTPCT_EL0); -} - -/* Set up the timer on the boot CPU (late init function) */ -int __init init_xen_time(void) -{ - int res; - unsigned int i; /* Retrieve all IRQs for the timer */ for ( i = TIMER_PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++ ) @@ -113,7 +143,31 @@ int __init init_xen_time(void) panic("Timer: Unable to retrieve IRQ %u from the device tree", i); timer_irq[i] = res; } +} + +void __init preinit_xen_time(void) +{ + int res; + + /* Initialize all the generic timers presented in GTDT */ + if ( acpi_disabled ) + preinit_dt_xen_time(); + else + preinit_acpi_xen_time(); + + if ( !cpu_khz ) + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; + + res = platform_init_time(); + if ( res ) + panic("Timer: Cannot initialize platform timer"); + boot_count = READ_SYSREG64(CNTPCT_EL0); +} + +/* Set up the timer on the boot CPU (late init function) */ +int __init init_xen_time(void) +{ /* Check that this CPU supports the Generic Timer interface */ if ( !cpu_has_gentimer ) panic("CPU does not support the Generic Timer v1 interface");