From patchwork Wed Feb 3 02:02:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Stultz X-Patchwork-Id: 61052 Delivered-To: patches@linaro.org Received: by 10.112.43.199 with SMTP id y7csp28372lbl; Tue, 2 Feb 2016 18:02:22 -0800 (PST) X-Received: by 10.98.43.73 with SMTP id r70mr52363520pfr.4.1454464942775; Tue, 02 Feb 2016 18:02:22 -0800 (PST) Return-Path: Received: from mail-pa0-x22d.google.com (mail-pa0-x22d.google.com. [2607:f8b0:400e:c03::22d]) by mx.google.com with ESMTPS id h6si5605592pfd.5.2016.02.02.18.02.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Feb 2016 18:02:22 -0800 (PST) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c03::22d as permitted sender) client-ip=2607:f8b0:400e:c03::22d; Authentication-Results: mx.google.com; spf=pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c03::22d as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-pa0-x22d.google.com with SMTP id cy9so4354258pac.0 for ; Tue, 02 Feb 2016 18:02:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=31/IiNwcAua0x2HcqRdxIDwfapWYk55w5R8QXzc7yQo=; b=KtRsTpFAEtOYI/l6kwmqjHZ9SiVorkyntGv0jnkucG8USH6OgG8BaFglLgQqhr1XD3 4EUHaeutgA1/M2DZ5hYlYyOHU8ccEIILcssvYu1Hjm5VP2KeksTq+t2NZ4I4SM8H1jQb tr0WZHjniRPN2ls1bB8RriWb2/q0tUZhTEphg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=31/IiNwcAua0x2HcqRdxIDwfapWYk55w5R8QXzc7yQo=; b=lNprv/V+SBYqWTwZ5o5wSwHoFPjKWi8x3XAvnq0Ym/tUIQLH9/g2/IrNJKxUDtLETQ YgzOwOztwiJho55E1yzcOyX8MzPIdENPdk+BPTtHNgoIimsHftlLmRrU2Lmc+GvmpE5M DgCJxWEQz2VJeFTJdKmvGah9Xy5FokyQT1R6oZyYdbVnbkJAez6ZAnWGeNWgJxIby7gS uHu6io7TpDUktSoV6/yFN/Ga55MApNCrq/a0fUDs4JNItqW+i0U1H86suwciXcINxyPy Q5c9CPzC5vABukAtgqXfDP9PYLfMbJhpJ39xAjhtdFQwanqmoHBO//T2DaPFI2roPwoy dXKQ== X-Gm-Message-State: AG10YORS7gts2RXfn3oRleiu0WK5p5OlXvmg6eRXUI5Apg44FIRJoOD8bsPuTh/q3wJQs+tZrQA= X-Received: by 10.66.155.167 with SMTP id vx7mr52360920pab.109.1454464942442; Tue, 02 Feb 2016 18:02:22 -0800 (PST) Return-Path: Received: from localhost.localdomain (c-76-115-103-22.hsd1.or.comcast.net. [76.115.103.22]) by smtp.gmail.com with ESMTPSA id pu3sm5480604pac.9.2016.02.02.18.02.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Feb 2016 18:02:21 -0800 (PST) From: John Stultz To: Guodong Xu Cc: John Stultz Subject: [PATCH 1/2] hikey: clk: Add RTC clock for pl031 hi6220 Date: Tue, 2 Feb 2016 18:02:16 -0800 Message-Id: <1454464937-17622-1-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 1.9.1 Adds clk support for the pl031 RTC on hi6220 (swiped from similar logic in the 4.1 tree) Signed-off-by: John Stultz --- drivers/clk/hisilicon/clk-hi6220.c | 1 + include/dt-bindings/clock/hi6220-clock.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 023ac3e..56b219e 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -69,6 +69,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, }, { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, }, { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, + { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, }, }; static struct hisi_clock_data *clk_data_ao; diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 70ee383..8df5a24 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -55,8 +55,8 @@ #define HI6220_TIMER7_PCLK 34 #define HI6220_TIMER8_PCLK 35 #define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 +#define HI6220_RTC0_PCLK 41 +#define HI6220_AO_NR_CLKS 48 /* clk in Hi6220 systrl */ /* gate clock */