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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:21 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:18 +0000 Message-Id: <20180305160415.16760-1-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 00/57] New VGIC(-v2) implementation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" tl;dr: Coarse changelog below, individual patches have changelogs as well. This is an updated version of the new VGIC-v2 implementation. Compared to the RFC posted a month ago, many things have been changed to address the review comments. The most important things are: - The GICv3 redistributor cleanup patches at the beginning of this series have been fixed to address the previous review comments. - The "physical-follows-virtual" IRQ affinity functionality is now implemented. - Trying to shrink data structures, namely struct vgic_irq. - Removing not needed data structures and code stubs for parts dealing with ITS or the CPU interface emulation. - Renaming of some existing Xen function names to be more readable. - Use existing LR accessor functions when updating/sycing LR content. - Dumping extra save/restore_state functions when syncing to/from LRs. - Fixes and adjustments to locking scheme. - Improving ACTIVE MMIO handling, documenting limitations. - Many minor changes to address whitespace issues, data types (uint32_t vs. u32, unsigned vs. signed), extended comments and commit messages. An summarising changelog can be found below, each individual patch has its own changelog as well. There are some things that have (still) not been covered yet: - struct VCPU still allocates two pages now. We can either limit this to ARM64 && the new VGIC, or try to look if we can allocate some parts of struct vcpu instead of embedding sub-structures into it. - vGICv3 support is not implemented, but should be fairly straight-forward to add, as the design incorporated this already. Will look at this next. - There is a possible DOS vector on the VCPU ap_list, which holds pending vIRQs. A guest can make this list rather long, which forces the hypervisor to hold the list lock when iterating the list. This should be bounded by the number of emulated vIRQs though, and there are ideas how to mitigate this issue. Those fixes would be posted on top as fixes later. - There is no ITS support, though the VGIC code itself is more ready for that than the old VGIC ever was. However due to differences between the Xen and KVM architecture the ITS bits are not easy to port over to Xen. Cheers, Andre ===================== During development of the Dom0 ITS MSI support last year we realised that the existing GIC interrupt controller emulation has some shortcomings. After some tries to fix those in the existing code, it was agreed upon that the problems are fundamental and a new implementation based on the "new VGIC" in KVM is the best choice. This is the first drop of this new VGIC implementation. It lives in the xen/arch/arm/vgic/ directory and is written to be a compile time option, so people can choose whether to use the new VGIC or the existing implementation. This is just for a transitional period, the old VGIC is expected to be removed after confidence in the new implementation has grown. This series starts with some GICv3 redistributor cleanup, which I posted before. I need to incorporate the comments from the list, but for now I left those patches as it from the previous post. Starting with patch 07 there are some more cleanups and preparations for the existing VGIC/GIC code. A big part of those patches are preparations to properly support level triggered interrupts. This is one of the biggest problems in the existing VGIC, which only correctly emulates edge triggered IRQs. This affects both arch code and some users like the timer and the event channel. Starting with patch 27 we plumb in the new VGIC then. This is done in a new directory, with all the files actually not wired into the build system until the very last patch. The idea is to split the series into reviewable chunks without resorting to nasty hacks to keep bisectability. The code was forked from Linux' virt/kvm/arm/vgic/, as of 4.14-rc7, plus some recent changes to improve support for level triggered and hardware mapped interrupts, which is what we use heavily in Dom0. The code was heavily adapted to fit into Xen, starting with using the Xen coding style and using Xen structure and variable names (struct domain instead of struct kvm, for instance). Where interfacing functions were similar enough, they were changed over to the existing Xen name and prototypes (for instance kvm_vgic_create() was renamed to domain_vgic_register()). As far as possible the code layout and split was re-used from KVM, so patches in Linux should be relatively easy to port into Xen. Due to the mentioned changes this can not be done easily in an automatic way, but it should be not too complicated to extract the gist of the patch and re-apply this to our code base. The actual VGIC code splits into several parts: - The core is the struct vgic_irq, which holds every information about a virtual IRQ, including a per-IRQ lock. Also there is on (ordered) per-VCPU list (ap_list), which links the interrupts to be considered by a VCPU. There are functions to deal with queuing and removing IRQs from those lists safely, obeying the locking order. (patches 27-30) - There are functions to push vIRQs on a VCPU list to the list registers, and handle their state changes. (patches 31-33) - The distributor MMIO emulation is using separate functions per register, also having read and write split. (patches 34-44) - There are functions to deal with Xen specialities. (patches 45-51) - The data structures and the wiring of the emulation into the hypervisor and the guests are done in vgic-init.c. (patches 52-55) - Finally patch 57 enables the build of the new VGIC. This requires to increase the size limit for struct vcpu in patch 56. Andre Changelog RFC ... v1: - observe review comments on GICv3 redistributor patches - implement physical-follows-virtual IRQ affinity - actually implement arch_move_irq() - move max_domain_vcpus() into vgic.c, to make it VGIC specific - improved many commit messages - add ACKs so far - added and extended many comments - use C99 data types (uint32_t) - use unsigned data types - use symbolic names for constants - white space fixes (indentation mostly) - adapt later patches to changes earlier in the series (renames etc.) - use 32 bit data types where sufficient - add helper functions as requested (for instance gicv2/3_peek/poke_irq) - use struct irq_desc * in interface of hardware facing functions - rename some existing Xen function names to be more readable - rename new header file from arm_vgic.h to new_vgic.h - drop code or variables dealing with unimplemented features (ITS, CPU i/f) - reorder struct vgic_irq and use bitfield to shrink data structure size - remove not needed functions (gic_clear_lrs(), save/restore_state()) - add ASSERTS as requested - add locking where missing (dump_vgic_info, read pending state, enabling GIC) - keep Linux coding style for list_sort.c - add set_pending_state() GIC abstraction function - factor out and use kick_vcpu() - use frame number instead of physical address - use existing LR accessor functions, drop GICH_ accesses from vgic-v2.c - skip already disabled/enabled IRQs and setting enabled state - use PRODUCT_ID_XEN - simplify and clarify on ACTIVE bit MMIO accesses - use interface for HCR bit changes - iterate over set CPU bits in SGI injection handler Andre Przywara (57): tools: ARM: vGICv3: Avoid inserting optional DT properties ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol ARM: GICv3: use hardware GICv3 redistributor values for Dom0 ARM: GICv3: simplify GICv3 redistributor stride handling ARM: vGICv3: always use architected redist stride ARM: vGICv3: remove rdist_stride from VGIC structure ARM: VGIC: rename gic_inject() and gic_clear_lrs() ARM: VGIC: Move gic_remove_from_lr_pending() prototype ARM: VGIC: Move domain_max_vcpus() to be VGIC specific ARM: VGIC: rename gic_event_needs_delivery() ARM: VGIC: change to level-IRQ compatible IRQ injection interface ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist ARM: VGIC: reorder prototypes in vgic.h ARM: VGIC: Introduce gic_get_nr_lrs() ARM: GICv2: Extend and adjust register definitions ARM: GICv3: rename HYP interface definitions to use ICH_ prefix ARM: Introduce kick_vcpu() ARM: GICv2: introduce gicv2_poke_irq() ARM: GICv3: poke_irq: make RWP optional ARM: GICv2: fix GICH_V2_LR definitions ARM: GICv2: extend LR read/write functions to cover EOI and source ARM: GIC: Allow tweaking the active and pending state of an IRQ ARM: GIC: allow reading pending state of a hardware IRQ ARM: timer: Handle level triggered IRQs correctly ARM: evtchn: Handle level triggered IRQs correctly ARM: vPL011: Use the VGIC's level triggered IRQs handling if available ARM: new VGIC: Add data structure definitions ARM: new VGIC: Add acccessor to new struct vgic_irq instance ARM: new VGIC: Implement virtual IRQ injection ARM: new VGIC: Add IRQ sorting ARM: new VGIC: Add IRQ sync/flush framework ARM: new VGIC: Add GICv2 world switch backend ARM: new VGIC: Implement vgic_vcpu_pending_irq ARM: new VGIC: Add MMIO handling framework ARM: new VGIC: Add GICv2 MMIO handling framework ARM: new VGIC: Add CTLR, TYPER and IIDR handlers ARM: new VGIC: Add ENABLE registers handlers ARM: new VGIC: Add PENDING registers handlers ARM: new VGIC: Add ACTIVE registers handlers ARM: new VGIC: Add PRIORITY registers handlers ARM: new VGIC: Add CONFIG registers handlers ARM: new VGIC: Add TARGET registers handlers ARM: new VGIC: Add SGIR register handler ARM: new VGIC: Add SGIPENDR register handlers ARM: new VGIC: Handle hardware mapped IRQs ARM: new VGIC: Add event channel IRQ handling ARM: new VGIC: Handle virtual IRQ allocation/reservation ARM: new VGIC: Dump virtual IRQ info ARM: new VGIC: provide system register emulation stub ARM: new VGIC: Implement arch_move_irqs() ARM: new VGIC: Add preliminary stub implementation ARM: new VGIC: vgic-init: register VGIC ARM: new VGIC: vgic-init: implement vgic_init ARM: new VGIC: vgic-init: implement map_resources ARM: new VGIC: Add vgic_v2_enable ARM: allocate two pages for struct vcpu ARM: VGIC: wire new VGIC(-v2) files into Xen build system tools/libxl/libxl_arm.c | 8 - xen/arch/arm/Kconfig | 6 +- xen/arch/arm/Makefile | 10 +- xen/arch/arm/domain.c | 34 +- xen/arch/arm/gic-v2.c | 76 ++- xen/arch/arm/gic-v3-lpi.c | 2 +- xen/arch/arm/gic-v3.c | 147 ++++-- xen/arch/arm/gic-vgic.c | 16 +- xen/arch/arm/gic.c | 15 + xen/arch/arm/irq.c | 2 +- xen/arch/arm/smp.c | 14 + xen/arch/arm/time.c | 38 +- xen/arch/arm/traps.c | 11 +- xen/arch/arm/vgic-v3.c | 40 +- xen/arch/arm/vgic.c | 67 ++- xen/arch/arm/vgic/vgic-init.c | 256 ++++++++++ xen/arch/arm/vgic/vgic-mmio-v2.c | 317 ++++++++++++ xen/arch/arm/vgic/vgic-mmio.c | 651 +++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 148 ++++++ xen/arch/arm/vgic/vgic-v2.c | 303 ++++++++++++ xen/arch/arm/vgic/vgic.c | 996 ++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 78 +++ xen/arch/arm/vpl011.c | 6 +- xen/arch/arm/vtimer.c | 4 +- xen/common/Makefile | 1 + xen/common/list_sort.c | 157 ++++++ xen/include/asm-arm/domain.h | 87 +--- xen/include/asm-arm/event.h | 3 +- xen/include/asm-arm/gic.h | 55 ++- xen/include/asm-arm/gic_v3_defs.h | 54 ++- xen/include/asm-arm/new_vgic.h | 198 ++++++++ xen/include/asm-arm/smp.h | 3 + xen/include/asm-arm/vgic.h | 150 +++++- xen/include/public/arch-arm.h | 1 - xen/include/xen/list_sort.h | 11 + xen/include/xen/timer.h | 2 + 36 files changed, 3666 insertions(+), 301 deletions(-) create mode 100644 xen/arch/arm/vgic/vgic-init.c create mode 100644 xen/arch/arm/vgic/vgic-mmio-v2.c create mode 100644 xen/arch/arm/vgic/vgic-mmio.c create mode 100644 xen/arch/arm/vgic/vgic-mmio.h create mode 100644 xen/arch/arm/vgic/vgic-v2.c create mode 100644 xen/arch/arm/vgic/vgic.c create mode 100644 xen/arch/arm/vgic/vgic.h create mode 100644 xen/common/list_sort.c create mode 100644 xen/include/asm-arm/new_vgic.h create mode 100644 xen/include/xen/list_sort.h