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+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CTU CAN FD Open-source IP Core Device Tree Bindings
+
+description: |
+ Open-source CAN FD IP core developed at the Czech Technical University in Prague
+
+ The core sources and documentation on project page
+ [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
+ [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf
+
+ Integration in Xilinx Zynq SoC based system together with
+ OpenCores SJA1000 compatible controllers
+ [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
+ Martin Jerabek dimploma thesis with integration and testing
+ framework description
+ [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf
+
+maintainers:
+ - Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ - Ondrej Ille <ondrej.ille@gmail.com>
+ - Martin Jerabek <martin.jerabek01@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: ctu,ctucanfd
+ - const: ctu,canfd-2
+ - const: ctu,ctucanfd
+
+ reg:
+ description:
+ mapping into bus address space, offset and size
+ maxItems: 1
+
+ interrupts:
+ description: |
+ interrupt source. For Zynq SoC system, format is <(is_spi) (number) (type)>
+ where is_spi defines if it is SPI (shared peripheral) interrupt,
+ the second number is translated to the vector by addition of 32
+ on Zynq-7000 systems and type is IRQ_TYPE_LEVEL_HIGH (4) for Zynq.
+ maxItems: 1
+
+ clocks:
+ description: |
+ phandle of reference clock (100 MHz is appropriate
+ for FPGA implementation on Zynq-7000 system).
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ ctu_can_fd_0: can@43c30000 {
+ compatible = "ctu,ctucanfd";
+ interrupts = <0 30 4>;
+ clocks = <&clkc 15>;
+ reg = <0x43c30000 0x10000>;
+ };