diff mbox series

[net-next,2/2] r8169: change the L0/L1 entrance latencies for RTL8106e

Message ID 20210806091556.1297186-376-nic_swsd@realtek.com
State New
Headers show
Series [net-next,1/2] Revert "r8169: avoid link-up interrupt issue on RTL8106e if user enables ASPM" | expand

Commit Message

Hayes Wang Aug. 6, 2021, 9:15 a.m. UTC 
The original L0 and L1 entrance latencies of RTL8106e are 4us. And
they cause the delay of link-up interrupt when enabling ASPM. Change
the L0 entrance latency to 7us and L1 entrance latency to 32us. Then,
they could avoid the issue.

Tested-by: Koba Ko <koba.ko@canonical.com>
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
---
 drivers/net/ethernet/realtek/r8169_main.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Heiner Kallweit Aug. 6, 2021, 9:27 p.m. UTC | #1 
On 06.08.2021 11:15, Hayes Wang wrote:
> The original L0 and L1 entrance latencies of RTL8106e are 4us. And
> they cause the delay of link-up interrupt when enabling ASPM. Change
> the L0 entrance latency to 7us and L1 entrance latency to 32us. Then,
> they could avoid the issue.
> 
> Tested-by: Koba Ko <koba.ko@canonical.com>
> Signed-off-by: Hayes Wang <hayeswang@realtek.com>
> ---
>  drivers/net/ethernet/realtek/r8169_main.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
> index d2647036b1e7..2c643ec36bdf 100644
> --- a/drivers/net/ethernet/realtek/r8169_main.c
> +++ b/drivers/net/ethernet/realtek/r8169_main.c
> @@ -3502,6 +3502,9 @@ static void rtl_hw_start_8106(struct rtl8169_private *tp)
>  	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
>  	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
>  
> +	/* The default value is 0x13. Change it to 0x2f */
> +	rtl_csi_access_enable(tp, 0x2f);

Most chip versions use rtl_set_def_aspm_entry_latency() that sets
the value to 0x27. Does this value also work for RTL8106e?
Then we could simply use the same call here.

Can you explain how the L0 and L1 times in us map to the
register value? Then we could add a function that doesn't work
with a magic value but takes the L0 and L1 times in us as
parameter.

> +
>  	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
>  
>  	/* disable EEE */
>
Hayes Wang Aug. 7, 2021, 3:50 a.m. UTC | #2 
Heiner Kallweit <hkallweit1@gmail.com>
> Sent: Saturday, August 7, 2021 5:28 AM

[...]
> Most chip versions use rtl_set_def_aspm_entry_latency() that sets

> the value to 0x27. Does this value also work for RTL8106e?


No, it doesn't work.

> Can you explain how the L0 and L1 times in us map to the

> register value? Then we could add a function that doesn't work

> with a magic value but takes the L0 and L1 times in us as

> parameter.


L0 (bit 0~2):
	0: 1us
	1: 2us
	2: 3us
	3: 4us
	4: 5us
	5: 6us
	6: 7us
	7: 7us (The maximum is 7us)

L1 (bit 3~5):
	0: 1us
	1: 2us
	2: 4us
	3: 8us
	4: 16us
	5: 32us
	6: 64us
	7: 64us (The maximum is 64us)

Best Regards,
Hayes
diff mbox series

Patch

diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index d2647036b1e7..2c643ec36bdf 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -3502,6 +3502,9 @@  static void rtl_hw_start_8106(struct rtl8169_private *tp)
 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
 
+	/* The default value is 0x13. Change it to 0x2f */
+	rtl_csi_access_enable(tp, 0x2f);
+
 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
 
 	/* disable EEE */