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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id c3sm5455237edn.16.2021.05.14.14.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 May 2021 14:00:28 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [PATCH net-next v6 13/25] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327 Date: Fri, 14 May 2021 23:00:03 +0200 Message-Id: <20210514210015.18142-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210514210015.18142-1-ansuelsmth@gmail.com> References: <20210514210015.18142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 10 ++++++++++ drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index b598930190e1..10e3e1ca7e95 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -930,6 +930,16 @@ qca8k_setup(struct dsa_switch *ds) } } + /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ + if (priv->switch_id == QCA8K_ID_QCA8327) { + mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); + qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, + QCA8K_GLOBAL_FC_GOL_XON_THRES_S | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, + mask); + } + /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 42d90836dffa..eceeacfe2c5d 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -168,6 +168,12 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) + #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)