Message ID | 20210406221107.1004-5-kabel@kernel.org |
---|---|
State | New |
Headers | show |
Series | net: phy: marvell10g updates | expand |
> @@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev) > val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); > if (val < 0) > return val; > - priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) == > - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH); > + priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) == > + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH); > > /* Enable EDPD mode - saving 600mW */ > return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); > -- So it appears that mv3310_config_init() should not be used with the mv88x2110. Did i miss somewhere where mv3310_drivers was changed so it actually does not use it? Andrew
On Wed, 7 Apr 2021 02:10:24 +0200 Andrew Lunn <andrew@lunn.ch> wrote: > > @@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev) > > val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); > > if (val < 0) > > return val; > > - priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) == > > - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH); > > + priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) == > > + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH); > > > > /* Enable EDPD mode - saving 600mW */ > > return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); > > -- > > So it appears that mv3310_config_init() should not be used with the > mv88x2110. Did i miss somewhere where mv3310_drivers was changed so it > actually does not use it? > > Andrew This patch series makes it later so that mv3310_config_init() correctly initializes even 2210 (this is done in patch 07/18). The function then calls chip->get_mactype() and chip->init_interface() methods, which are different for 3310 than for 2110. I am thinking about whether all the functions which are same for all the chips should be renamed from mv3310_* to mv10g_* This would rename mv3310_config_init to mv10g_config_init which would be more correct. What do you think? Marek
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 881a0717846e..7552a658a513 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -78,10 +78,10 @@ enum { /* Vendor2 MMD registers */ MV_V2_PORT_CTRL = 0xf001, - MV_V2_PORT_CTRL_SWRST = BIT(15), - MV_V2_PORT_CTRL_PWRDOWN = BIT(11), - MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7, - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6, + MV_V2_PORT_CTRL_PWRDOWN = BIT(11), + MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), + MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6, /* Temperature control/read registers (88X3310 only) */ MV_V2_TEMP_CTRL = 0xf08a, MV_V2_TEMP_CTRL_MASK = 0xc000, @@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev) return ret; return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, - MV_V2_PORT_CTRL_SWRST); + MV_V2_33X0_PORT_CTRL_SWRST); } static int mv3310_reset(struct phy_device *phydev, u32 unit) @@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev) val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); if (val < 0) return val; - priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) == - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH); + priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) == + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH); /* Enable EDPD mode - saving 600mW */ return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
Rename port control registers to indicate that they are valid only for 88X33x0, not for 88E21x0. Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/net/phy/marvell10g.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)