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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o19sm1554136ilt.24.2020.11.05.10.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 10:14:25 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 10/13] net: ipa: only enable GSI IEOB IRQs when needed Date: Thu, 5 Nov 2020 12:14:04 -0600 Message-Id: <20201105181407.8006-11-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201105181407.8006-1-elder@linaro.org> References: <20201105181407.8006-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org A GSI channel must be started in order to use it to perform a transfer data (or command) transaction. And the only time we'll see an IEOB interrupt is if we send a transaction to a started channel. Therefore we do not need to have the IEOB interrupt type enabled until at least one channel has been started. And once the last started channel has been stopped, we can disable the IEOB interrupt type again. We already enable the IEOB interrupt for a particular channel only when it is started. Extend that by having the IEOB interrupt *type* be enabled only when at least one channel is in STARTED state. Disallow all channels from triggering the IEOB interrupt in gsi_irq_setup(). We only enable an channel's interrupt when needed, so there is no longer any need to zero the channel mask in gsi_irq_disable(). Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 4ab1d89f642ea..aae8ea852349d 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -258,6 +258,7 @@ static void gsi_irq_setup(struct gsi *gsi) iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); } /* Turn off all GSI interrupts when we're all done */ @@ -269,11 +270,16 @@ static void gsi_irq_teardown(struct gsi *gsi) static void gsi_irq_ieob_enable(struct gsi *gsi, u32 evt_ring_id) { + bool enable_ieob = !gsi->ieob_enabled_bitmap; u32 val; gsi->ieob_enabled_bitmap |= BIT(evt_ring_id); val = gsi->ieob_enabled_bitmap; iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); + + /* Enable the interrupt type if this is the first channel enabled */ + if (enable_ieob) + gsi_irq_type_enable(gsi, GSI_IEOB); } static void gsi_irq_ieob_disable(struct gsi *gsi, u32 evt_ring_id) @@ -281,6 +287,11 @@ static void gsi_irq_ieob_disable(struct gsi *gsi, u32 evt_ring_id) u32 val; gsi->ieob_enabled_bitmap &= ~BIT(evt_ring_id); + + /* Disable the interrupt type if this was the last enabled channel */ + if (!gsi->ieob_enabled_bitmap) + gsi_irq_type_disable(gsi, GSI_IEOB); + val = gsi->ieob_enabled_bitmap; iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); } @@ -296,10 +307,6 @@ static void gsi_irq_enable(struct gsi *gsi) iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); gsi->type_enabled_bitmap |= BIT(GSI_GLOB_EE); - /* Each IEOB interrupt is enabled (later) as needed by channels */ - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); - gsi->type_enabled_bitmap |= BIT(GSI_IEOB); - /* We don't use inter-EE channel or event interrupts */ /* Never enable GSI_BREAK_POINT */ @@ -318,7 +325,6 @@ static void gsi_irq_disable(struct gsi *gsi) gsi_irq_type_update(gsi); iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); }