From patchwork Fri May 29 04:40:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Kirsher X-Patchwork-Id: 218239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56012C433DF for ; Fri, 29 May 2020 04:40:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3E97A20C09 for ; Fri, 29 May 2020 04:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbgE2Ekg (ORCPT ); Fri, 29 May 2020 00:40:36 -0400 Received: from mga03.intel.com ([134.134.136.65]:40323 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726319AbgE2EkT (ORCPT ); Fri, 29 May 2020 00:40:19 -0400 IronPort-SDR: d7Z0mD8pV8YdpuDbKLxWuuRR4toy4xJW5XETx1oRt8bUCglHs8H5EeoGyUd2ThAJVlCID3RDM8 964AYNgK8L5g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2020 21:40:06 -0700 IronPort-SDR: KNb5iaduasiWCxC5ZTWsjFP5toTebWrqLlHn45NS10bZmx/q2nvDJQCcOaWLfz80KZHyKjuTvY K4pi2tnqoxjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,447,1583222400"; d="scan'208";a="414850936" Received: from jtkirshe-desk1.jf.intel.com ([134.134.177.86]) by orsmga004.jf.intel.com with ESMTP; 28 May 2020 21:40:05 -0700 From: Jeff Kirsher To: davem@davemloft.net Cc: Sasha Neftin , netdev@vger.kernel.org, nhorman@redhat.com, sassmann@redhat.com, Aaron Brown , Jeff Kirsher Subject: [net-next 14/17] igc: Add Receive Error Counter Date: Thu, 28 May 2020 21:40:01 -0700 Message-Id: <20200529044004.3725307-15-jeffrey.t.kirsher@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200529044004.3725307-1-jeffrey.t.kirsher@intel.com> References: <20200529044004.3725307-1-jeffrey.t.kirsher@intel.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Sasha Neftin Receive error counter reflect total number of non-filtered packets received with errors. This includes: CRC error, symbol error, Rx data error and carrier extend error. Signed-off-by: Sasha Neftin Tested-by: Aaron Brown Signed-off-by: Jeff Kirsher --- drivers/net/ethernet/intel/igc/igc_mac.c | 1 + drivers/net/ethernet/intel/igc/igc_main.c | 1 + drivers/net/ethernet/intel/igc/igc_regs.h | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c index 9de70a24cb9e..a5a087e1ac02 100644 --- a/drivers/net/ethernet/intel/igc/igc_mac.c +++ b/drivers/net/ethernet/intel/igc/igc_mac.c @@ -241,6 +241,7 @@ void igc_clear_hw_cntrs_base(struct igc_hw *hw) rd32(IGC_MCC); rd32(IGC_LATECOL); rd32(IGC_COLC); + rd32(IGC_RERC); rd32(IGC_DC); rd32(IGC_SEC); rd32(IGC_RLEC); diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 662f06a647e6..e0c45ffa12c4 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -3740,6 +3740,7 @@ void igc_update_stats(struct igc_adapter *adapter) adapter->stats.tpt += rd32(IGC_TPT); adapter->stats.colc += rd32(IGC_COLC); + adapter->stats.colc += rd32(IGC_RERC); adapter->stats.algnerrc += rd32(IGC_ALGNERRC); diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h index a3e4ec922948..7ac3b611708c 100644 --- a/drivers/net/ethernet/intel/igc/igc_regs.h +++ b/drivers/net/ethernet/intel/igc/igc_regs.h @@ -134,6 +134,7 @@ #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */ #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */ #define IGC_COLC 0x04028 /* Collision Count - R/clr */ +#define IGC_RERC 0x0402C /* Receive Error Count - R/clr */ #define IGC_DC 0x04030 /* Defer Count - R/clr */ #define IGC_TNCRS 0x04034 /* Tx-No CRS - R/clr */ #define IGC_SEC 0x04038 /* Sequence Error Count - R/clr */