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Miller" Cc: netdev@vger.kernel.org, Julien Beraud Subject: [PATCH 2/2] net: stmmac: Fix sub-second increment Date: Tue, 14 Apr 2020 11:10:03 +0200 Message-Id: <20200414091003.7629-2-julien.beraud@orolia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200414091003.7629-1-julien.beraud@orolia.com> References: <20200414091003.7629-1-julien.beraud@orolia.com> X-ClientProxiedBy: LO2P265CA0318.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a4::18) To AM5PR06MB3043.eurprd06.prod.outlook.com (2603:10a6:206:3::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from julien.spectracom.local (2a01:cb00:87a9:7d00:9d00:f9d3:1f5a:64cc) by LO2P265CA0318.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a4::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2900.15 via Frontend Transport; Tue, 14 Apr 2020 09:11:46 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [2a01:cb00:87a9:7d00:9d00:f9d3:1f5a:64cc] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0441c4ad-b3aa-4a67-88ef-08d7e053dbe6 X-MS-TrafficTypeDiagnostic: AM5PR06MB3057:|AM5PR06MB3057: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 0373D94D15 X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM5PR06MB3043.eurprd06.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(10009020)(4636009)(376002)(396003)(366004)(39850400004)(346002)(136003)(4326008)(6506007)(81156014)(110136005)(6486002)(2906002)(316002)(5660300002)(8936002)(186003)(8676002)(16526019)(478600001)(66946007)(86362001)(6666004)(52116002)(36756003)(1076003)(107886003)(66476007)(44832011)(6512007)(2616005)(66556008); DIR:OUT; SFP:1101; Received-SPF: None (protection.outlook.com: orolia.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /fk+81g1J6g4KibzDvrmUKx92NIrbiNS+ZFuaG6ydvYabiMDZRxkYh2BZUx1kO9qvl0uwYtKotMuCyngy2GiTxiuNo4XdFDM7M/dCfwaixmITNb3Xy1EzBObmwb3b4GM6MM6DL6vblYOhBYI/0T5MFjG5WSszf0mkqGSzbWYYB3aOh1yV7mnMCMghOnHiJR6LEoWbz+lq4us9BxeLObstocczYFdqRDuyWzbE2ozAVZnYHir+TVSMSOdLgfd3WbWStgOVE2uzPOQOUL32MactaOEKdgHZhwGQai5mIY6IRJE8CcK8UcfKYf21rJyL7qaR3HiJjwNBF40HpsK5OB1t9O9U/N71M8JhPiwrs3k/IVGhSY0DbFz3+DdNhs/49RHzyxVit48c3uwXJwqbyZLm2dR1H8XKc6vyV7QB8j6sF/Ia9VcpS8BTu4cgtNHW+h3 X-MS-Exchange-AntiSpam-MessageData: WiAsJwe2eD2SuBlq+KPdJsSPXFt1hzWPTtHB+ljMMfzwQzJ6fHBD4RUNV3NiQH9Grf+tHz7TJ4+kxsdfB9nwr29k8s7QvKTrnhQ/DOzf7QPBENKYHf/3PQr5k+paptMzgGlf+0zdsOY8PD9Sm/iYh6oYHFVJ939alxtVYt2zyoVAl0WdhBXGGP41h0iXcnz6ecNewxCYBHCe4/a8Om6R8w== X-OriginatorOrg: orolia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0441c4ad-b3aa-4a67-88ef-08d7e053dbe6 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2020 09:11:47.4349 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a263030c-9c1b-421f-9471-1dec0b29c664 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YmHfEWPGLDJurgu+kszIJGLtAMx6wJtCdcYG31uzh34FK0/ujcIOVxpj6PLqrWQXFdBx8g2PHKpM7KuECe7zoSK6hf7eMVt5JeNsz0ynjBA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR06MB3057 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org In fine adjustement mode, which is the current default, the sub-second increment register is the number of nanoseconds that wil be added to the clock when the accumulator overflows. At each clock cycle, the value of the addend register is added to the accumulator. Currently, we use 20ns = 1e09ns / 50MHz as this value whatever the frequency of the ptp clock actually is. The adjustment is then done on the addend register, only incrementing every X clock cycles X being the ratio between 50MHz and ptp_clock_rate (addend = 2^31 * 50MHz/ptp_clock_rate). First of all there is a bug that was already solved in the past in that it should be 40ns = 2e09ns / 50MHz - (the accumulator can only overflow once every 2 additions) Even with this issue fixed, this has following consequences : - The resolution of the timestamping clock is limited to 40ns while it is not needed, thus limiting the accuracy of the timestamping to 40ns. - In case the frequency of the ptp clock is inferior to 50MHz, the addend value will be set to 0 and the clock will simply not work. Fix this by setting sub-second increment to 2e09ns / ptp_clock_rate and setting the default value of addend to mid-range = 2^31. By doing this we can reach the best possible resolution in the timestamps, only incrementing the clock by the minimum possible value. This will also work for frequencies below 50MHz (for instance using the internal osc1 clock at 25MHz for socfpga platforms). Signed-off-by: Julien Beraud --- drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 10 ++++++---- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 ++--------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c index fcf080243a0f..2438c7bbc7c9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c @@ -27,12 +27,14 @@ static void config_sub_second_increment(void __iomem *ioaddr, unsigned long data; u32 reg_value; - /* For GMAC3.x, 4.x versions, convert the ptp_clock to nano second - * formula = (1/ptp_clock) * 1000000000 - * where ptp_clock is 50MHz if fine method is used to update system + /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second + * increment to twice the number of nanoseconds of a clock cycle. + * Setting the default addend value to mid range will make the + * accumulator overflow once every 2 clock cycles, thus adding twice + * the length of a clock cycle to the clock time. */ if (value & PTP_TCR_TSCFUPDT) - data = (1000000000ULL / 50000000); + data = (2000000000ULL / ptp_clock); else data = (1000000000ULL / ptp_clock); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index e6898fd5223f..4ceddfa64b1d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -511,7 +511,6 @@ static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) struct stmmac_priv *priv = netdev_priv(dev); struct hwtstamp_config config; struct timespec64 now; - u64 temp = 0; u32 ptp_v2 = 0; u32 tstamp_all = 0; u32 ptp_over_ipv4_udp = 0; @@ -698,19 +697,13 @@ static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) stmmac_config_sub_second_increment(priv, priv->ptpaddr, priv->plat->clk_ptp_rate, xmac, &sec_inc); - temp = div_u64(1000000000ULL, sec_inc); /* Store sub second increment and flags for later use */ priv->sub_second_inc = sec_inc; priv->systime_flags = value; - /* calculate default added value: - * formula is : - * addend = (2^32)/freq_div_ratio; - * where, freq_div_ratio = 1e9ns/sec_inc - */ - temp = (u64)(temp << 32); - priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); + /* set default addend to mid-range */ + priv->default_addend = (1 << 31); stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); /* initialize system time */