From patchwork Tue May 2 09:59:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 98429 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1791326qgf; Tue, 2 May 2017 03:02:39 -0700 (PDT) X-Received: by 10.98.152.78 with SMTP id q75mr30713748pfd.256.1493719359406; Tue, 02 May 2017 03:02:39 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t73si17178428pfa.66.2017.05.02.03.02.39; Tue, 02 May 2017 03:02:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751302AbdEBKCh (ORCPT + 6 others); Tue, 2 May 2017 06:02:37 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:5846 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750983AbdEBKCe (ORCPT ); Tue, 2 May 2017 06:02:34 -0400 Received: from 172.30.72.55 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.55]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AMU50688; Tue, 02 May 2017 18:01:34 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.153) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Tue, 2 May 2017 18:00:04 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 2/2] net: ixgbe: disable RO depending on the root port flags Date: Tue, 2 May 2017 10:59:26 +0100 Message-ID: <1493719166-9036-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1493719166-9036-1-git-send-email-gabriele.paoloni@huawei.com> References: <1493719166-9036-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.153] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.590858FF.01AE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f638d4d59da76d0eb74da7454f1c5339 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: gabriele paoloni Intel ixgbe drivers currently disable relaxed ordering at compilation time depending on the host architecture. This is wrong as RO support depends either on the root complex implementation and/or on the EP itself and/or both. This patch checks at runtime the root port flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to be set in order to disable RO. Signed-off-by: Gabriele Paoloni --- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 35 ++++++++++++++----------- 1 file changed, 20 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index 094e1d6..597cb7b 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -342,6 +342,8 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) { u32 i; + struct pci_dev *root; + struct ixgbe_adapter *adapter; /* Clear the rate limiters */ for (i = 0; i < hw->mac.max_tx_queues; i++) { @@ -350,25 +352,28 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; i < hw->mac.max_tx_queues; i++) { - u32 regval; + adapter = container_of(hw, struct ixgbe_adapter, hw); + root = pci_find_pcie_root_port(adapter->pdev); - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); - } + if (root && (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING)) { + /* Disable relaxed ordering */ + for (i = 0; i < hw->mac.max_tx_queues; i++) { + u32 regval; - for (i = 0; i < hw->mac.max_rx_queues; i++) { - u32 regval; + regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); + regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); + } + + for (i = 0; i < hw->mac.max_rx_queues; i++) { + u32 regval; - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); + regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | + IXGBE_DCA_RXCTRL_HEAD_WRO_EN); + IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); + } } -#endif return 0; }