From patchwork Sat Apr 1 07:25:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 96537 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1058147qgd; Sat, 1 Apr 2017 00:26:51 -0700 (PDT) X-Received: by 10.84.209.133 with SMTP id y5mr7713214plh.25.1491031610989; Sat, 01 Apr 2017 00:26:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si7403635plb.41.2017.04.01.00.26.50; Sat, 01 Apr 2017 00:26:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751034AbdDAH0s (ORCPT + 6 others); Sat, 1 Apr 2017 03:26:48 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5293 "EHLO dggrg01-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750787AbdDAH0q (ORCPT ); Sat, 1 Apr 2017 03:26:46 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ALV84946; Sat, 01 Apr 2017 15:26:12 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Sat, 1 Apr 2017 15:26:02 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH net-next 4/4] ixgbe: enable IXGBE_ALLOW_RELAXED_ORDER for ARM64 Date: Sat, 1 Apr 2017 15:25:54 +0800 Message-ID: <1491031554-19516-5-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> References: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.58DF5614.0027, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3c06e6e5719d20fa4225224f0b60ab3f Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The IXGBE_ALLOW_RELAXED_ORDER will enable Relaxed Ordering (RO) which allows transactions that do not have any order of completion requirements to complete more efficiently compare to the Stricted Ordering (SO) for ixgbe net card. Some architecture will see high write-to-memory performance when RO is enabled on the data transactions just like the SPARC did. The aarch64 could both support Relaxed Ordering (RO) and Stricted Ordering (SO), so enable this config could get much more better performance, didn't see any adverse effects. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.0 diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig index 33ef2b6..6743b7e 100644 --- a/drivers/net/ethernet/intel/Kconfig +++ b/drivers/net/ethernet/intel/Kconfig @@ -276,7 +276,7 @@ config FM10K will be called fm10k. MSI-X interrupt support is required config IXGBE_ALLOW_RELAXED_ORDER - bool "Intel(R) 10GbE PCI Express adapters Enable Relaxed Ordering" if SPARC - default y if SPARC + bool "Intel(R) 10GbE PCI Express adapters Enable Relaxed Ordering" if (SPARC || ARM64) + default y if (SPARC || ARM64) endif # NET_VENDOR_INTEL