From patchwork Sat Apr 1 07:25:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 96539 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1058197qgd; Sat, 1 Apr 2017 00:27:03 -0700 (PDT) X-Received: by 10.98.211.143 with SMTP id z15mr6303591pfk.46.1491031623581; Sat, 01 Apr 2017 00:27:03 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si7403635plb.41.2017.04.01.00.27.03; Sat, 01 Apr 2017 00:27:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750849AbdDAH0q (ORCPT + 6 others); Sat, 1 Apr 2017 03:26:46 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5292 "EHLO dggrg01-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750801AbdDAH0p (ORCPT ); Sat, 1 Apr 2017 03:26:45 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ALV84943; Sat, 01 Apr 2017 15:26:11 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Sat, 1 Apr 2017 15:26:01 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH net-next 2/4] ixgbe: ixgbevf: Clear the CONFIG_SPARC for ixgbevf and 82598 Date: Sat, 1 Apr 2017 15:25:52 +0800 Message-ID: <1491031554-19516-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> References: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.58DF5614.0023, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 892776acf77c11ab34267f0423c8fb6e Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The CONFIG_SPARC in ixgbevf and ixgbe_82598 is only used to enable relaxed ordering, the CONFIG_IXBGE_WANT_RELAXED_ORDER already did this, so rename this config for the same setting. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 4 ++-- drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 1.9.0 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 523f9d0..c7f95ae 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -175,7 +175,7 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) **/ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) { -#ifndef CONFIG_SPARC +#ifndef CONFIG_IXGBE_ALLOW_RELAXED_ORDER u32 regval; u32 i; #endif @@ -183,7 +183,7 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) ret_val = ixgbe_start_hw_generic(hw); -#ifndef CONFIG_SPARC +#ifndef CONFIG_IXGBE_ALLOW_RELAXED_ORDER /* Disable relaxed ordering */ for (i = 0; ((i < hw->mac.max_tx_queues) && (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c index 80bab26..c27932d 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c @@ -1713,7 +1713,7 @@ static void ixgbevf_configure_rx_ring(struct ixgbevf_adapter *adapter, IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx), ring->count * sizeof(union ixgbe_adv_rx_desc)); -#ifndef CONFIG_SPARC +#ifndef CONFIG_IXGBE_ALLOW_RELAXED_ORDER /* enable relaxed ordering */ IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), IXGBE_DCA_RXCTRL_DESC_RRO_EN);