[v3,0/2] net: Add LiteETH network driver

This adds a driver for the LiteX network device, LiteEth.

v3 Updates the bindings to describe the slots in a way that makes more
sense for the hardware, instead of trying to fit some existing
properties. The driver is updated to use these bindings, and fix some
issues pointed out by Gabriel.

v2 Addresses feedback from Jakub, with detailed changes in each patch.

It also moves to the litex register accessors so the system works on big
endian litex platforms. I tested with mor1k on an Arty A7-100T.

I have removed the mdio aspects of the driver as they are not needed for
basic operation. I will continue to work on adding support in the
future, but I don't think it needs to block the mac driver going in.

The binding describes the mdio registers, and has been fixed to not show
any warnings against dtschema master.

LiteEth is a simple driver for the FPGA based Ethernet device used in various
RISC-V, PowerPC's microwatt, OpenRISC's mor1k and other FPGA based
systems on chip.

Joel Stanley (2):
  dt-bindings: net: Add bindings for LiteETH
  net: Add driver for LiteX's LiteETH network interface

 .../bindings/net/litex,liteeth.yaml           | 100 ++++++
 drivers/net/ethernet/Kconfig                  |   1 +
 drivers/net/ethernet/Makefile                 |   1 +
 drivers/net/ethernet/litex/Kconfig            |  27 ++
 drivers/net/ethernet/litex/Makefile           |   5 +
 drivers/net/ethernet/litex/litex_liteeth.c    | 317 ++++++++++++++++++
 6 files changed, 451 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
 create mode 100644 drivers/net/ethernet/litex/Kconfig
 create mode 100644 drivers/net/ethernet/litex/Makefile
 create mode 100644 drivers/net/ethernet/litex/litex_liteeth.c

On Wed, Aug 25, 2021 at 10:16:54PM +0930, Joel Stanley wrote:
> LiteETH is a small footprint and configurable Ethernet core for FPGA
> based system on chips.
> 
> The hardware is parametrised by the size and number of the slots in it's
> receive and send buffers. These are described as properties, with the
> commonly used values set as the default.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v2:
>  - Fix dtschema check warning relating to registers
>  - Add names to the registers to make it easier to distinguish which is
>    what region
>  - Add mdio description
>  - Include ethernet-controller parent description
> v3:
>  - Define names for reg-names
>  - update example to match common case
>  - describe the hardware using slots and slot sizes. This is how the
>    hardware is pramaterised, and it makes more sense than trying to use
>    the rx/tx-fifo-size properties
> ---
>  .../bindings/net/litex,liteeth.yaml           | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> new file mode 100644
> index 000000000000..62911b8e913c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LiteX LiteETH ethernet device
> +
> +maintainers:
> +  - Joel Stanley <joel@jms.id.au>
> +
> +description: |
> +  LiteETH is a small footprint and configurable Ethernet core for FPGA based
> +  system on chips.
> +
> +  The hardware source is Open Source and can be found on at
> +  https://github.com/enjoy-digital/liteeth/.
> +
> +allOf:
> +  - $ref: ethernet-controller.yaml#
> +
> +properties:
> +  compatible:
> +    const: litex,liteeth
> +
> +  reg:
> +    minItems: 3

Don't need minItems if it is equal to 'items' length.

> +    items:
> +      - description: MAC registers
> +      - description: MDIO registers
> +      - description: Packet buffer
> +
> +  reg-names:
> +    minItems: 3

And here.

With that fixed:

Reviewed-by: Rob Herring <robh@kernel.org>

> +    items:
> +      - const: mac
> +      - const: mdio
> +      - const: buffer
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  litex,rx-slots:
> +    description: Number of slots in the receive buffer
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 1
> +    default: 2
> +
> +  litex,tx-slots:
> +    description: Number of slots in the transmit buffer
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 1
> +    default: 2
> +
> +  litex,slot-size:
> +    description: Size in bytes of a slot in the tx/rx buffer
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0x800
> +    default: 0x800
> +
> +  mac-address: true
> +  local-mac-address: true
> +  phy-handle: true
> +
> +  mdio:
> +    $ref: mdio.yaml#
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    mac: ethernet@8020000 {
> +        compatible = "litex,liteeth";
> +        reg = <0x8021000 0x100>,
> +              <0x8020800 0x100>,
> +              <0x8030000 0x2000>;
> +        reg-names = "mac", "mdio", "buffer";
> +        litex,rx-slots = <2>;
> +        litex,tx-slots = <2>;
> +        litex,slot-size = <0x800>;
> +        interrupts = <0x11 0x1>;
> +        phy-handle = <&eth_phy>;
> +
> +        mdio {
> +          #address-cells = <1>;
> +          #size-cells = <0>;
> +
> +          eth_phy: ethernet-phy@0 {
> +            reg = <0>;
> +          };
> +        };
> +    };
> +...
> +
> +#  vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
> -- 
> 2.33.0
> 
>