From patchwork Fri Jun 19 19:15:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 217509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 516BBC433E1 for ; Fri, 19 Jun 2020 19:16:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36B1E20C09 for ; Fri, 19 Jun 2020 19:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733208AbgFSTQL (ORCPT ); Fri, 19 Jun 2020 15:16:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733165AbgFSTQJ (ORCPT ); Fri, 19 Jun 2020 15:16:09 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00AE3C0617B9 for ; Fri, 19 Jun 2020 12:16:06 -0700 (PDT) Received: from ramsan ([IPv6:2a02:1810:ac12:ed20:e0be:48f2:cba4:1407]) by xavier.telenet-ops.be with bizsmtp id t7Fx220034UASYb017FxCJ; Fri, 19 Jun 2020 21:16:05 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1jmMUX-0002JR-28; Fri, 19 Jun 2020 21:15:57 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1jmMUX-0006V6-0C; Fri, 19 Jun 2020 21:15:57 +0200 From: Geert Uytterhoeven To: Sergei Shtylyov , "David S . Miller" , Jakub Kicinski , Rob Herring Cc: Andrew Lunn , Oleksij Rempel , Philippe Schenker , Florian Fainelli , Heiner Kallweit , Kazuya Mizuguchi , Wolfram Sang , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 0/5] ravb: Add support for explicit internal clock delay configuration Date: Fri, 19 Jun 2020 21:15:49 +0200 Message-Id: <20200619191554.24942-1-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi all, Some Renesas EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This caused issues with PHY drivers that implement PHY internal delays properly[1]. Hence a backwards-compatible workaround was added by masking the PHY mode[2]. This RFC patch series implements the next step of the plan outlined in [3], and adds proper support for explicit configuration of the MAC internal clock delays using new "renesas,[rt]xc-delay-ps" properties. If none of these properties is present, the driver falls back to the old handling. The series consists of 4 parts: 1. DT binding update documenting the new properties, 2. A preparatory improvement, 3. Driver update implementing support for the new properties, 4. DT updates, one for R-Car Gen3 and RZ/G2 SoC families each. Note that patches 4 and 5 depend on patch 3, and must not be applied before that dependency has hit upstream. Impacted, tested: - Salvator-X(S) with R-Car H3 ES1.0 and ES2.0, M3-W, and M3-N. Not impacted, tested: - Ebisu with R-Car E3. Impacted, not tested: - Salvator-X(S) with other SoC variants, - ULCB with R-Car H3/M3-W/M3-N variants, - V3MSK and Eagle with R-Car V3M, - Draak with R-Car V3H, - HiHope RZ/G2[MN] with RZ/G2M or RZ/G2N. Thanks for your comments! References: [1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") [2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting delays twice"). https://lore.kernel.org/r/20200529122540.31368-1-geert+renesas@glider.be/ [3] https://lore.kernel.org/r/CAMuHMdU+MR-2tr3-pH55G0GqPG9HwH3XUd=8HZxprFDMGQeWUw@mail.gmail.com/ Geert Uytterhoeven (5): dt-bindings: net: renesas,ravb: Document internal clock delay properties ravb: Split delay handling in parsing and applying ravb: Add support for explicit internal clock delay configuration arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling .../devicetree/bindings/net/renesas,ravb.txt | 29 ++++++----- .../boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 + .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 3 +- .../arm64/boot/dts/renesas/r8a77970-v3msk.dts | 3 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + .../boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- drivers/net/ethernet/renesas/ravb.h | 5 +- drivers/net/ethernet/renesas/ravb_main.c | 52 ++++++++++++++----- 19 files changed, 86 insertions(+), 31 deletions(-)