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[54.197.127.237]) by mx.google.com with ESMTP id s5si2615050qta.132.2017.12.22.03.05.46; Fri, 22 Dec 2017 03:05:47 -0800 (PST) Received-SPF: pass (google.com: domain of lng-odp-bounces@lists.linaro.org designates 54.197.127.237 as permitted sender) client-ip=54.197.127.237; Authentication-Results: mx.google.com; spf=pass (google.com: domain of lng-odp-bounces@lists.linaro.org designates 54.197.127.237 as permitted sender) smtp.mailfrom=lng-odp-bounces@lists.linaro.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=yandex.ru Received: by lists.linaro.org (Postfix, from userid 109) id AE16D6175C; Fri, 22 Dec 2017 11:05:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id B8286616FA; Fri, 22 Dec 2017 11:00:47 +0000 (UTC) X-Original-To: lng-odp@lists.linaro.org Delivered-To: lng-odp@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4B6886151F; Fri, 22 Dec 2017 11:00:30 +0000 (UTC) Received: from forward102p.mail.yandex.net (forward102p.mail.yandex.net [77.88.28.102]) by lists.linaro.org (Postfix) with ESMTPS id 14E4060997 for ; Fri, 22 Dec 2017 11:00:20 +0000 (UTC) Received: from mxback7o.mail.yandex.net (mxback7o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::21]) by forward102p.mail.yandex.net (Yandex) with ESMTP id 296EB430377C for ; Fri, 22 Dec 2017 14:00:19 +0300 (MSK) Received: from smtp2o.mail.yandex.net (smtp2o.mail.yandex.net [2a02:6b8:0:1a2d::26]) by mxback7o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id HbxPAitDAK-0JtqBdPI; Fri, 22 Dec 2017 14:00:19 +0300 Received: by smtp2o.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id EWw1bAbGHJ-0I5GAeUZ; Fri, 22 Dec 2017 14:00:18 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client certificate not present) From: Github ODP bot To: lng-odp@lists.linaro.org Date: Fri, 22 Dec 2017 14:00:14 +0300 Message-Id: <1513940417-8765-2-git-send-email-odpbot@yandex.ru> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513940417-8765-1-git-send-email-odpbot@yandex.ru> References: <1513940417-8765-1-git-send-email-odpbot@yandex.ru> Github-pr-num: 359 Subject: [lng-odp] [PATCH CATERPILLAR v3 1/4] linux-gen: add memory-mapped I/O access API X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "The OpenDataPlane \(ODP\) List" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: lng-odp-bounces@lists.linaro.org Sender: "lng-odp" From: Mykyta Iziumtsev Signed-off-by: Mykyta Iziumtsev --- /** Email created from pull request 359 (MykytaI:caterpillar_mdev_auxiliary) ** https://github.com/Linaro/odp/pull/359 ** Patch: https://github.com/Linaro/odp/pull/359.patch ** Base sha: 63fd88635cc10caaa02fdccd3f52c9494487bdd2 ** Merge commit sha: 236ad276c55ab617e42fb2b92f40afdb8c4bb1ee **/ include/odp/drv/spec/mmio.h | 145 +++++++++++++++++++++ platform/linux-generic/include/odp/drv/mmio.h | 179 ++++++++++++++++++++++++++ scripts/checkpatch.pl | 1 + 3 files changed, 325 insertions(+) create mode 100644 include/odp/drv/spec/mmio.h create mode 100644 platform/linux-generic/include/odp/drv/mmio.h diff --git a/include/odp/drv/spec/mmio.h b/include/odp/drv/spec/mmio.h new file mode 100644 index 000000000..35807637b --- /dev/null +++ b/include/odp/drv/spec/mmio.h @@ -0,0 +1,145 @@ +/* Copyright (c) 2017, Linaro Limited + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file + * + * API to access memory-mapped I/O. + * + */ + +#ifndef ODPDRV_MMIO_H_ +#define ODPDRV_MMIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup odpdrv_mmio ODPDRV MMIO + * @{ + */ + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 8-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u8le_write(uint8_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 8-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u8be_write(uint8_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 16-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u16le_write(uint16_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 16-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u16be_write(uint16_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 32-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u32le_write(uint32_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 32-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u32be_write(uint32_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 64-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u64le_write(uint64_t value, volatile void *addr); + +/** + * Convert endianness and write value to MMIO + * @param value cpu native 64-bit value to write to MMIO + * @param addr MMIO address to write at + */ +void odpdrv_mmio_u64be_write(uint64_t value, volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 8-bit value + */ +uint8_t odpdrv_mmio_u8le_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 8-bit value + */ +uint8_t odpdrv_mmio_u8be_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 16-bit value + */ +uint16_t odpdrv_mmio_u16le_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 16-bit value + */ +uint16_t odpdrv_mmio_u16be_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 32-bit value + */ +uint32_t odpdrv_mmio_u32le_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 32-bit value + */ +uint32_t odpdrv_mmio_u32be_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 64-bit value + */ +uint64_t odpdrv_mmio_u64le_read(volatile void *addr); + +/** + * Read from MMIO and convert endianness + * @param addr MMIO address to read at + * @return cpu native 64-bit value + */ +uint64_t odpdrv_mmio_u64be_read(volatile void *addr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/linux-generic/include/odp/drv/mmio.h b/platform/linux-generic/include/odp/drv/mmio.h new file mode 100644 index 000000000..4c4596abe --- /dev/null +++ b/platform/linux-generic/include/odp/drv/mmio.h @@ -0,0 +1,179 @@ +/* Copyright (c) 2017, Linaro Limited + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file + * + * API to access memory-mapped I/O. + */ + +#ifndef ODPDRV_PLAT_MMIO_H_ +#define ODPDRV_PLAT_MMIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** @ingroup odpdrv_mmio ODPDRV MMIO + * @{ + */ + +/* for use with type checkers such as sparse */ +#ifdef __CHECKER__ +/** @internal MMIO attribute */ +#define __odpdrv_mmio __attribute__((noderef, address_space(2))) +#else +/** @internal MMIO attribute */ +#define __odpdrv_mmio +#endif + +#define odpdrv_io_mb() __asm__ __volatile__("" ::: "memory") +#define odpdrv_io_rmb() __asm__ __volatile__("" ::: "memory") +#define odpdrv_io_wmb() __asm__ __volatile__("" ::: "memory") + +static inline void +odpdrv_mmio_u8le_write(uint8_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile uint8_t *)addr = value; +} + +static inline void +odpdrv_mmio_u8be_write(uint8_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_mmio_u8le_write(value, addr); +} + +static inline void +odpdrv_mmio_u16le_write(uint16_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u16le_t *)addr = odp_cpu_to_le_16(value); +} + +static inline void +odpdrv_mmio_u16be_write(uint16_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u16be_t *)addr = odp_cpu_to_be_16(value); +} + +static inline void +odpdrv_mmio_u32le_write(uint32_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u32le_t *)addr = odp_cpu_to_le_32(value); +} + +static inline void +odpdrv_mmio_u32be_write(uint32_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u32be_t *)addr = odp_cpu_to_be_32(value); +} + +static inline void +odpdrv_mmio_u64le_write(uint64_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u64le_t *)addr = odp_cpu_to_le_64(value); +} + +static inline void +odpdrv_mmio_u64be_write(uint64_t value, volatile void __odpdrv_mmio *addr) +{ + odpdrv_io_wmb(); + *(__odp_force volatile odp_u64be_t *)addr = odp_cpu_to_be_64(value); +} + +static inline uint8_t +odpdrv_mmio_u8le_read(volatile void __odpdrv_mmio *addr) +{ + uint8_t value = *(__odp_force volatile uint8_t *)addr; + + odpdrv_io_rmb(); + return value; +} + +static inline uint8_t +odpdrv_mmio_u8be_read(volatile void __odpdrv_mmio *addr) +{ + return odpdrv_mmio_u8le_read(addr); +} + +static inline uint16_t +odpdrv_mmio_u16le_read(volatile void __odpdrv_mmio *addr) +{ + uint16_t value = + odp_le_to_cpu_16(*(__odp_force volatile odp_u16le_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +static inline uint16_t +odpdrv_mmio_u16be_read(volatile void __odpdrv_mmio *addr) +{ + uint16_t value = + odp_be_to_cpu_16(*(__odp_force volatile odp_u16be_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +static inline uint32_t +odpdrv_mmio_u32le_read(volatile void __odpdrv_mmio *addr) +{ + uint32_t value = + odp_le_to_cpu_32(*(__odp_force volatile odp_u32le_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +static inline uint32_t +odpdrv_mmio_u32be_read(volatile void __odpdrv_mmio *addr) +{ + uint32_t value = + odp_be_to_cpu_32(*(__odp_force volatile odp_u32be_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +static inline uint64_t +odpdrv_mmio_u64le_read(volatile void __odpdrv_mmio *addr) +{ + uint64_t value = + odp_le_to_cpu_64(*(__odp_force volatile odp_u64le_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +static inline uint64_t +odpdrv_mmio_u64be_read(volatile void __odpdrv_mmio *addr) +{ + uint64_t value = + odp_be_to_cpu_64(*(__odp_force volatile odp_u64be_t *)addr); + + odpdrv_io_rmb(); + return value; +} + +/** + * @} + */ + +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 16316b928..9c256e29a 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -257,6 +257,7 @@ sub hash_show_words { __kernel| __force| __iomem| + __odpdrv_mmio| __must_check| __init_refok| __kprobes|