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[54.225.227.206]) by mx.google.com with ESMTPS id r8si2372524wif.54.2014.10.16.06.56.18 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 16 Oct 2014 06:56:19 -0700 (PDT) Received-SPF: none (google.com: lng-odp-bounces@lists.linaro.org does not designate permitted sender hosts) client-ip=54.225.227.206; Received: from localhost ([127.0.0.1] helo=ip-10-35-177-41.ec2.internal) by ip-10-35-177-41.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XelXN-0008NR-1e; Thu, 16 Oct 2014 13:56:17 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by ip-10-35-177-41.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XelX8-0008MS-Vk for lng-odp@lists.linaro.org; Thu, 16 Oct 2014 13:56:03 +0000 Received: by mail-pa0-f43.google.com with SMTP id lf10so3499310pab.30 for ; Thu, 16 Oct 2014 06:55:57 -0700 (PDT) X-Received: by 10.68.219.164 with SMTP id pp4mr1371281pbc.143.1413467757484; Thu, 16 Oct 2014 06:55:57 -0700 (PDT) Received: from yogesh-Dell-System-Vostro-3360.Airtel4Grouter.cpe ([14.140.2.178]) by mx.google.com with ESMTPSA id 16sm19899221pdj.42.2014.10.16.06.55.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Oct 2014 06:55:56 -0700 (PDT) From: Yogesh Tillu To: lng-odp@lists.linaro.org Date: Thu, 16 Oct 2014 19:22:05 +0530 Message-Id: <1413467525-30304-4-git-send-email-yogesh.tillu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413467525-30304-1-git-send-email-yogesh.tillu@linaro.org> References: <1413467525-30304-1-git-send-email-yogesh.tillu@linaro.org> X-Topics: patch Cc: Yogesh Tillu Subject: [lng-odp] [PATCH] To read PMU cycle counter through vDSO Path X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: lng-odp-bounces@lists.linaro.org Sender: lng-odp-bounces@lists.linaro.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: yogesh.tillu@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Signed-off-by: Yogesh Tillu --- arch/arm64/kernel/vdso/Makefile | 6 +++--- arch/arm64/kernel/vdso/vdso.lds.S | 5 +++++ arch/arm64/kernel/vdso/vdso_perfc.c | 20 ++++++++++++++++++++ 3 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/kernel/vdso/vdso_perfc.c diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile index 6d20b7d..4fde490 100644 --- a/arch/arm64/kernel/vdso/Makefile +++ b/arch/arm64/kernel/vdso/Makefile @@ -5,7 +5,7 @@ # Heavily based on the vDSO Makefiles for other archs. # -obj-vdso := gettimeofday.o note.o sigreturn.o +obj-vdso := gettimeofday.o note.o sigreturn.o armpmu.o # Build rules targets := $(obj-vdso) vdso.so vdso.so.dbg @@ -43,8 +43,8 @@ $(obj)/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE $(call if_changed,vdsosym) # Assembly rules for the .S files -$(obj-vdso): %.o: %.S - $(call if_changed_dep,vdsoas) +#$(obj-vdso): %.o: %.S +# $(call if_changed_dep,vdsoas) # Actual build commands quiet_cmd_vdsold = VDSOL $@ diff --git a/arch/arm64/kernel/vdso/vdso.lds.S b/arch/arm64/kernel/vdso/vdso.lds.S index 8154b8d..8cb56e0 100644 --- a/arch/arm64/kernel/vdso/vdso.lds.S +++ b/arch/arm64/kernel/vdso/vdso.lds.S @@ -90,6 +90,11 @@ VERSION __kernel_gettimeofday; __kernel_clock_gettime; __kernel_clock_getres; + /* ADD YOUR VDSO STUFF HERE */ + perf_read_counter; + __vdso_perf_read_counter; + perf_open_counter; + __vdso_perf_open_counter; local: *; }; } diff --git a/arch/arm64/kernel/vdso/vdso_perfc.c b/arch/arm64/kernel/vdso/vdso_perfc.c new file mode 100644 index 0000000..c363d64 --- /dev/null +++ b/arch/arm64/kernel/vdso/vdso_perfc.c @@ -0,0 +1,20 @@ +#include + +int perf_read_counter(void) + __attribute__((weak, alias("__vdso__perf_read_counter"))); +int perf_open_counter(void) + __attribute__((weak, alias("__vdso__perf_open_counter"))); + +#define ARMV8_PMCNTENSET_EL0_ENABLE (1<<31) /**< Enable Perf count reg */ + +__attribute__((no_instrument_function)) int __vdso__perf_read_counter(void) +{ +int ret = 0; +asm volatile("mrs %0, pmccntr_el0" : "=r" (ret)); +return ret; +} + +__attribute__((no_instrument_function)) void __vdso__perf_open_counter(void) +{ +asm volatile("msr pmcntenset_el0, %0" : : "r" (ARMV8_PMCNTENSET_EL0_ENABLE)); +}