From patchwork Thu Sep 12 05:47:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 173653 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp1686562ilq; Wed, 11 Sep 2019 22:47:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqzbw2Sj4NHSWa0SDpwiDEBG/inTO/ECa5oGRd+COJJsd3g0mwJu64T2Qc9yvVDehciSAFV2 X-Received: by 2002:a50:fb0c:: with SMTP id d12mr39214124edq.275.1568267264973; Wed, 11 Sep 2019 22:47:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568267264; cv=none; d=google.com; s=arc-20160816; b=DqSg7CrC1Oy0Pp2dlFLwAvYxvy+ov+cTbqhUBb6GNXMfOpOFyKidbRnbYehgxV5NyC HiEqMrBiCZ8rfbmEr80Y0e5qOa8PepEcWTGtzXXboP9jo/gnwcEKnjZZeKa4UdyO1mhH I3uyrkjJoFS4599JqR38FuXP1odItmtI77OTCfx4kV8OGgg2i/kD942ISj5b+c26w6hj w1flXaskrhIKeZdfaow+ZDGaOJSjHwfF/hKc9maK7kKKTAxhnmxulKZFCNFAm29fZvUi AnrkSF9mlqp10IV0YgNqHMEnO6dwjeVsLxdrJRtvAwwI42JF8Ro+8Mzr05fz0ZaGkMvT vZjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=FH3mQ5WAiHQBqx7gMhW2IlaC7Eov6CFwaWdgd/wFtP0=; b=O4A+toyA0Un3Ba9Sfyf2CbbIeozScI8tRoOIzIapXneJFgfdefD/Tqlu+4pwwnFP4C 6F2uOesBKveiyuHyR6MkB92SCow1k4dLiDh2ihIBhnuHedviO4ydxToq/hALSlraI+13 PCBFFuFGhvGXAlVspkqlDlGX9r1gRzH7b13qdVXG/E4U1cb5hiRiJIGJuUXEZQqqTzZJ yP60IAuZeQ6ECfmvAUD5b9Ht5PV6VZlT9S9VcUoGk23AiXlrQYlbAdS/adoZORaXm1y3 bviL9sp8P2PqQEZXDjMGI1I+z9aRgD8qFwd3C27jjDayGyoNzJCWtP4iFFTuehOY1i1j xnKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PYvX2Jjy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y10si6320411edc.48.2019.09.11.22.47.44; Wed, 11 Sep 2019 22:47:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PYvX2Jjy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727835AbfILFrk (ORCPT + 27 others); Thu, 12 Sep 2019 01:47:40 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:42179 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725775AbfILFrk (ORCPT ); Thu, 12 Sep 2019 01:47:40 -0400 Received: by mail-pf1-f196.google.com with SMTP id w22so15225521pfi.9 for ; Wed, 11 Sep 2019 22:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=FH3mQ5WAiHQBqx7gMhW2IlaC7Eov6CFwaWdgd/wFtP0=; b=PYvX2Jjybf3jSculUvceSAy/P291IbUmtLltNSdFEVC5AYj8qeTuf0g8XKlMS2wcFI JtcmmkEyaOZvDhY5hJ9Mw5GYsAJjxQl7ktGVSZTDMr9d4jmDAXazAxnXDXMarAsnfNfU so7YUkqKuZ0GXE6lw8rxrW+vkoVyLDMFian057P0TYQ7iw+OBfmkhofNnApRI98Yuz5T HnVGGeArV8Z9PyZO4jnyFyG2xQmbHAa88kLYXZL/HD7WidVbCdAk4SCcmp+UKgcZo1Gs oilRMXiMwKRfzwrpQmqKvuHqV+otT1JA37Dt2gNR6PLb4u1gK6m7hyOF1TlIVKp7v528 Wk1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FH3mQ5WAiHQBqx7gMhW2IlaC7Eov6CFwaWdgd/wFtP0=; b=gcsx9oYVzrn7TGogGUtR4w5OYPea4PbD6w2MeClCphv7DOCFejXmryBEj/WBYiLWkn I103NPqCMb4DCtkVBLLsLf6Hl0ifdqhVvLhrmfPazZMj64s60y+MhsIa8RidhzfGOeke EHadybMx7G4e5Oqy3H2rnxXgvSFN6AYzuWlSRyoflWBK00s9btkYKI01G4kdACBNj4jz puACOVrJFchx+rrJjcwBR2rzMjMipwYaw5RmLe2BFITcQU2CMJLqbteR/dMwwGBFzCaY 08DiEh1cAWGHdrEcQZBdskxusdeAtNgccb6QrM6EAyFkzp2uJmBBM2nKrhpBo8cCh+Ue 2u4Q== X-Gm-Message-State: APjAAAWsgBi4iVEkJvQBpMamGfcPJ7nOoWUpjcTZW5taKceuVu2ORMk0 ktorB4n6daIylDT8tHJObN8B6A== X-Received: by 2002:a65:60d2:: with SMTP id r18mr35715713pgv.71.1568267259688; Wed, 11 Sep 2019 22:47:39 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id t14sm13228602pgb.33.2019.09.11.22.47.35 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Sep 2019 22:47:38 -0700 (PDT) From: Baolin Wang To: vkoul@kernel.org Cc: orsonzhai@gmail.com, zhang.lyra@gmail.com, dan.j.williams@intel.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, eric.long@unisoc.com, zhenfang.wang@unisoc.com, baolin.wang@linaro.org Subject: [PATCH] dmaengine: sprd: Fix the link-list pointer register configuration issue Date: Thu, 12 Sep 2019 13:47:18 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhenfang Wang We will set the link-list pointer register point to next link-list configuration's physical address, which can load DMA configuration from the link-list node automatically. But the link-list node's physical address can be larger than 32bits, and now Spreadtrum DMA driver only supports 32bits physical address, which may cause loading a incorrect DMA configuration when starting the link-list transfer mode. According to the DMA datasheet, we can use SRC_BLK_STEP register (bit28 - bit31) to save the high bits of the link-list node's physical address to fix this issue. Fixes: 4ac695464763 ("dmaengine: sprd: Support DMA link-list mode") Signed-off-by: Zhenfang Wang Signed-off-by: Baolin Wang --- drivers/dma/sprd-dma.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 1.7.9.5 diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c index 525dc73..a4a91f2 100644 --- a/drivers/dma/sprd-dma.c +++ b/drivers/dma/sprd-dma.c @@ -134,6 +134,10 @@ #define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0 #define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0) +/* SPRD DMA_SRC_BLK_STEP register definition */ +#define SPRD_DMA_LLIST_HIGH_MASK GENMASK(31, 28) +#define SPRD_DMA_LLIST_HIGH_SHIFT 28 + /* define DMA channel mode & trigger mode mask */ #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0) #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0) @@ -717,6 +721,7 @@ static int sprd_dma_fill_desc(struct dma_chan *chan, u32 int_mode = flags & SPRD_DMA_INT_MASK; int src_datawidth, dst_datawidth, src_step, dst_step; u32 temp, fix_mode = 0, fix_en = 0; + phys_addr_t llist_ptr; if (dir == DMA_MEM_TO_DEV) { src_step = sprd_dma_get_step(slave_cfg->src_addr_width); @@ -814,13 +819,16 @@ static int sprd_dma_fill_desc(struct dma_chan *chan, * Set the link-list pointer point to next link-list * configuration's physical address. */ - hw->llist_ptr = schan->linklist.phy_addr + temp; + llist_ptr = schan->linklist.phy_addr + temp; + hw->llist_ptr = lower_32_bits(llist_ptr); + hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) & + SPRD_DMA_LLIST_HIGH_MASK; } else { hw->llist_ptr = 0; + hw->src_blk_step = 0; } hw->frg_step = 0; - hw->src_blk_step = 0; hw->des_blk_step = 0; return 0; }