From patchwork Sun Dec 18 11:57:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 88375 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp686061qgi; Sun, 18 Dec 2016 03:57:06 -0800 (PST) X-Received: by 10.98.41.3 with SMTP id p3mr10853097pfp.22.1482062226136; Sun, 18 Dec 2016 03:57:06 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 63si14988393pfm.160.2016.12.18.03.57.05; Sun, 18 Dec 2016 03:57:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761221AbcLRL5D (ORCPT + 25 others); Sun, 18 Dec 2016 06:57:03 -0500 Received: from mail-io0-f179.google.com ([209.85.223.179]:34949 "EHLO mail-io0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757927AbcLRL5B (ORCPT ); Sun, 18 Dec 2016 06:57:01 -0500 Received: by mail-io0-f179.google.com with SMTP id h30so132819710iod.2 for ; Sun, 18 Dec 2016 03:57:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FjUcRTNBWHIKG5C8ZLMyW1GC0CLbS/k+pBpZadoMIbU=; b=k4Xb1x0zWV5LusQtX/aTw6YuuZDJC7Hm7X03tKXkL5pRRodxYv0GXANUZ4EpW//fui kji5ILn0TToWj8Cc9GgRydwO8sXDYfpTGOh/f5E3YrY0KA9sX4nJlWbVB/K1+VCh87Sx p+Do/YW6PCfIHo2lHPc9bNkTUl0aDHLhkSClo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FjUcRTNBWHIKG5C8ZLMyW1GC0CLbS/k+pBpZadoMIbU=; b=dL/OOWkr7THQiqr0+Hg4yAwpHzTyO+SmXAYdv6nxeHCbk9HjAQlLtZjH5g/k1ee0fb b2Rn7rnrR77zxeDpXR9SrA+MBDbvoGzmM/TTMmS5d9Z0XBkabNGBWOQmOeolRv9ez+5Z CWrKocDOB0uMFAUM643IGx4UO6T/hLe0xtFsdTI/78YgJJRyfWG7rcfcWt9WV1EcZ/VD i9PhpWCFIY4xfIL7lhs6I/kcxogr8NaX9qOToI5osueHAog4ol6NV1nF5v28W7quUQ4E Dva5hy2JQ0FVFbbOSWr6uFPiMBu3JWyemNvR1NP2HK3lIAJJKUrJ+/2TruGcmsnFRIR1 W7zQ== X-Gm-Message-State: AIkVDXJjj3VimSlaoMGk7nW1UuQuB+Fd9F+qHFUl/dCrBwjQpyjmztVf0j3Pr+J1ZuHBTBP/ZP00/yL98U5AgKcE X-Received: by 10.107.18.39 with SMTP id a39mr10240499ioj.45.1482062220847; Sun, 18 Dec 2016 03:57:00 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.198.67 with HTTP; Sun, 18 Dec 2016 03:57:00 -0800 (PST) In-Reply-To: <4112999.Nl7pxYH1YF@wuerfel> References: <20161216091457.2452987-1-arnd@arndb.de> <4112999.Nl7pxYH1YF@wuerfel> From: Ard Biesheuvel Date: Sun, 18 Dec 2016 11:57:00 +0000 Message-ID: Subject: Re: [PATCH] ARM: disallow ARM_THUMB for ARMv4 builds To: Arnd Bergmann Cc: Russell King , Nicolas Pitre , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Jonas Jensen Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16 December 2016 at 21:51, Arnd Bergmann wrote: > On Friday, December 16, 2016 5:20:22 PM CET Ard Biesheuvel wrote: >> >> Can't we use the old >> >> tst lr, #1 >> moveq pc, lr >> bx lr >> >> trick? (where bx lr needs to be emitted as a plain opcode to hide it >> from the assembler) >> > > Yes, that should work around the specific problem in theory, but back > when Jonas tried it, it still didn't work. There may also be other > problems in that configuration. > This should do the trick as well, I think: with the added benefit that we don't clobber the N and Z flags. Of course, this will result in all CPUs using a non-optimal sequence if support for v4 is compiled in. diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 9f157e7c51e7..3bfb32010234 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -835,7 +835,12 @@ ENDPROC(__switch_to) .macro usr_ret, reg #ifdef CONFIG_ARM_THUMB +#ifdef CONFIG_CPU_32v4 + str \reg, [sp, #-4]! + ldr pc, [sp], #4 +#else bx \reg +#endif #else ret \reg #endif