From patchwork Fri May 4 08:01:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 134966 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp538114lji; Fri, 4 May 2018 01:03:14 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqJcmSiAKrj7V5GBekN/aMynPWbj3tGF8Vt6ExaSJY4219h6eG1RKfa82IFv9gx4apQg2tC X-Received: by 2002:a63:755c:: with SMTP id f28-v6mr22232590pgn.30.1525420994232; Fri, 04 May 2018 01:03:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525420994; cv=none; d=google.com; s=arc-20160816; b=hVRdhYMBsAbgdjDYcuWG8FUcMqpdjmF7sYwnEoiFnIgzCajCXDmqMi0qUHOzCJ4qAk 39u52VqRV8eeSvcqgtvtKGre+Csl4/6xBS7JK+Tc8WzMr8LiiEFpsQa8mcwRObFW6XyP Y+BEaG3B/kj/yxLwACuOoSyjF3MKkFBc74B5EiCu1Zrdwyc2m6lud7PXgxUNeqmNVGEF 1kM46+NsaAe14KH3hFf7hRFvi1TAwd0g8b+Hv3wEydPIFfo8nwtHN84tbjFJ3D+rdnYf LQRU23HOW0cxtubGT4eGp4zDHaaKLTvbgWmXoo6GYPZzSDYoLxoqlWpqpKfG+d+fmgu9 Em9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=p0YDvvflUt8Nr7TfRd2mA3G/WtcULzNJukT3u6LhL/o=; b=x09zPhAApRLAYG53Hd+dIGK0wupk4o4nj09dJFDeVBIAH5k2qEYCKLbz2QSEUwVp58 yi4eUckMtZJsyXgA+7mZOfcg0J26jDqP9jkqP/PxijtgnMGE2NJtrghgCHUGCqYu/PI+ 74782ylSr62aDke44vnQ0Aa4mpeb15a9nLlyHp/TAADYqsaPxFzqviUq6lmOwXfq1MsH YRniKWoupHr/4KFm8HQEv01jtCuCF0Fa3DbDI/xmshQlG9rZ4ebxly5Q7La4X1zy/2fm s/xrqpoon4ZwTiq/43uxqdu/PlLu8XiwNlybNB4ci/ssgHEVEh1jKP9f7pAW7ZcYFGDH hvQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BR/m22Gq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s13-v6si3885250plq.464.2018.05.04.01.03.13; Fri, 04 May 2018 01:03:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BR/m22Gq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751663AbeEDIDI (ORCPT + 29 others); Fri, 4 May 2018 04:03:08 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:42132 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751522AbeEDICp (ORCPT ); Fri, 4 May 2018 04:02:45 -0400 Received: by mail-pf0-f194.google.com with SMTP id p14so5452739pfh.9 for ; Fri, 04 May 2018 01:02:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=p0YDvvflUt8Nr7TfRd2mA3G/WtcULzNJukT3u6LhL/o=; b=BR/m22GqyLjbIzTli/T3SL2nIr5rJRqrWHFKZ+eQO1hajJ8O8BUlgezWrFNDiGodCi 9WTYDv20wXMRXUtWEbeK7anzoRlWmti2PbN0M05iRqXUJ8+BL7yeq+oGOpmr2347Q2KM jSFEkEwDA8bLx1IG+aFpIa25bGj6FK28CRDOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=p0YDvvflUt8Nr7TfRd2mA3G/WtcULzNJukT3u6LhL/o=; b=B7A3OK25Owngk1X/l6Uuw71+FmceGTO/d7sq36hzYy5wZaLaOs1OBqHEEfbREWC8Z/ F9i5jJ6loOzxGfyvh11+XqJpmv9LiZOwik7e8xtSLCkE2146zZE9UcDsHxF8YaQlc0bm XugIH1tjS9g6UXaUMVzPPDRAzDfhhcAIaxWkuTi2bugpA24BBUaTrsPsWIK3kvdY/VYF bUUTA25VqMn2Av4oiInGBGCMKCUY9XTjf9B8TvDPZj+ZF0XJUGt8/fqOL0Ij7Dzqj9Hr KyvfAbm7qiw1A7s7HahD8sjM7lRg5g9e2D3Lq5isj1PVDs4y3zp3/W75T2lU07+Fuj0s 7cKA== X-Gm-Message-State: ALQs6tB5l6C3Hjpw4QTLFMkwg0FQNDt5O8IBXFAMtczQd8364JCTXjI8 402Tpn1OIHAMpDNS6yjsVZC+cw== X-Received: by 2002:a17:902:4301:: with SMTP id i1-v6mr26992249pld.280.1525420964981; Fri, 04 May 2018 01:02:44 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id 131sm29337519pfa.103.2018.05.04.01.02.41 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 May 2018 01:02:44 -0700 (PDT) From: Baolin Wang To: dan.j.williams@intel.com, vinod.koul@intel.com Cc: eric.long@spreadtrum.com, broonie@kernel.org, baolin.wang@linaro.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] dmaengine: sprd: Add Spreadtrum DMA configuration Date: Fri, 4 May 2018 16:01:37 +0800 Message-Id: <795030fce89ec55d015602fbf4594838a22a9094.1525420581.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Eric Long This patch adds the 'device_config' and 'device_prep_slave_sg' interfaces for users to configure DMA, as well as adding one 'struct sprd_dma_config' structure to save Spreadtrum DMA configuration for each DMA channel. Signed-off-by: Eric Long Signed-off-by: Baolin Wang --- drivers/dma/sprd-dma.c | 215 ++++++++++++++++++++++++++++++++++++++++++ include/linux/dma/sprd-dma.h | 4 + 2 files changed, 219 insertions(+) -- 1.7.9.5 diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c index a7a89fd..d7c7ffa 100644 --- a/drivers/dma/sprd-dma.c +++ b/drivers/dma/sprd-dma.c @@ -100,6 +100,8 @@ #define SPRD_DMA_DES_DATAWIDTH_OFFSET 28 #define SPRD_DMA_SWT_MODE_OFFSET 26 #define SPRD_DMA_REQ_MODE_OFFSET 24 +#define SPRD_DMA_WRAP_SEL_OFFSET 23 +#define SPRD_DMA_WRAP_EN_OFFSET 22 #define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0) #define SPRD_DMA_FIX_SEL_OFFSET 21 #define SPRD_DMA_FIX_EN_OFFSET 20 @@ -154,6 +156,35 @@ struct sprd_dma_chn_hw { u32 des_blk_step; }; +/* + * struct sprd_dma_config - DMA configuration structure + * @cfg: dma slave channel runtime config + * @src_addr: the source physical address + * @dst_addr: the destination physical address + * @block_len: specify one block transfer length + * @transcation_len: specify one transcation transfer length + * @src_step: source transfer step + * @dst_step: destination transfer step + * @wrap_ptr: wrap pointer address, once the transfer address reaches the + * 'wrap_ptr', the next transfer address will jump to the 'wrap_to' address. + * @wrap_to: wrap jump to address + * @req_mode: specify the DMA request mode + * @int_mode: specify the DMA interrupt type + */ +struct sprd_dma_config { + struct dma_slave_config cfg; + phys_addr_t src_addr; + phys_addr_t dst_addr; + u32 block_len; + u32 transcation_len; + u32 src_step; + u32 dst_step; + phys_addr_t wrap_ptr; + phys_addr_t wrap_to; + enum sprd_dma_req_mode req_mode; + enum sprd_dma_int_type int_mode; +}; + /* dma request description */ struct sprd_dma_desc { struct virt_dma_desc vd; @@ -164,6 +195,7 @@ struct sprd_dma_desc { struct sprd_dma_chn { struct virt_dma_chan vc; void __iomem *chn_base; + struct sprd_dma_config slave_cfg; u32 chn_num; u32 dev_id; struct sprd_dma_desc *cur_desc; @@ -552,6 +584,121 @@ static void sprd_dma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&schan->vc.lock, flags); } +static enum sprd_dma_datawidth +sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth) +{ + switch (buswidth) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + return SPRD_DMA_DATAWIDTH_1_BYTE; + + case DMA_SLAVE_BUSWIDTH_2_BYTES: + return SPRD_DMA_DATAWIDTH_2_BYTES; + + case DMA_SLAVE_BUSWIDTH_4_BYTES: + return SPRD_DMA_DATAWIDTH_4_BYTES; + + case DMA_SLAVE_BUSWIDTH_8_BYTES: + return SPRD_DMA_DATAWIDTH_8_BYTES; + + default: + return SPRD_DMA_DATAWIDTH_4_BYTES; + } +} + +static u32 sprd_dma_get_step(enum sprd_dma_datawidth datawidth) +{ + switch (datawidth) { + case SPRD_DMA_DATAWIDTH_1_BYTE: + return SPRD_DMA_BYTE_STEP; + + case SPRD_DMA_DATAWIDTH_2_BYTES: + return SPRD_DMA_SHORT_STEP; + + case SPRD_DMA_DATAWIDTH_4_BYTES: + return SPRD_DMA_WORD_STEP; + + case SPRD_DMA_DATAWIDTH_8_BYTES: + return SPRD_DMA_DWORD_STEP; + + default: + return SPRD_DMA_DWORD_STEP; + } +} + +static int sprd_dma_config(struct dma_chan *chan, struct sprd_dma_desc *sdesc, + struct sprd_dma_config *slave_cfg) +{ + struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan); + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_chn_hw *hw = &sdesc->chn_hw; + u32 fix_mode = 0, fix_en = 0, wrap_en = 0, wrap_mode = 0; + u32 src_datawidth, dst_datawidth; + + if (slave_cfg->cfg.slave_id) + schan->dev_id = slave_cfg->cfg.slave_id; + + hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; + hw->wrap_ptr = (u32)((slave_cfg->wrap_ptr & SPRD_DMA_LOW_ADDR_MASK) | + ((slave_cfg->src_addr >> SPRD_DMA_HIGH_ADDR_OFFSET) & + SPRD_DMA_HIGH_ADDR_MASK)); + hw->wrap_to = (u32)((slave_cfg->wrap_to & SPRD_DMA_LOW_ADDR_MASK) | + ((slave_cfg->dst_addr >> SPRD_DMA_HIGH_ADDR_OFFSET) & + SPRD_DMA_HIGH_ADDR_MASK)); + + hw->src_addr = (u32)(slave_cfg->src_addr & SPRD_DMA_LOW_ADDR_MASK); + hw->des_addr = (u32)(slave_cfg->dst_addr & SPRD_DMA_LOW_ADDR_MASK); + + if ((slave_cfg->src_step != 0 && slave_cfg->dst_step != 0) + || (slave_cfg->src_step | slave_cfg->dst_step) == 0) { + fix_en = 0; + } else { + fix_en = 1; + if (slave_cfg->src_step) + fix_mode = 1; + else + fix_mode = 0; + } + + if (slave_cfg->wrap_ptr && slave_cfg->wrap_to) { + wrap_en = 1; + if (slave_cfg->wrap_to == slave_cfg->src_addr) { + wrap_mode = 0; + } else if (slave_cfg->wrap_to == slave_cfg->dst_addr) { + wrap_mode = 1; + } else { + dev_err(sdev->dma_dev.dev, "invalid wrap mode\n"); + return -EINVAL; + } + } + + hw->intc = slave_cfg->int_mode | SPRD_DMA_CFG_ERR_INT_EN; + + src_datawidth = sprd_dma_get_datawidth(slave_cfg->cfg.src_addr_width); + dst_datawidth = sprd_dma_get_datawidth(slave_cfg->cfg.dst_addr_width); + hw->frg_len = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET | + dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET | + slave_cfg->req_mode << SPRD_DMA_REQ_MODE_OFFSET | + wrap_mode << SPRD_DMA_WRAP_SEL_OFFSET | + wrap_en << SPRD_DMA_WRAP_EN_OFFSET | + fix_mode << SPRD_DMA_FIX_SEL_OFFSET | + fix_en << SPRD_DMA_FIX_EN_OFFSET | + (slave_cfg->cfg.src_maxburst & SPRD_DMA_FRG_LEN_MASK); + + hw->blk_len = slave_cfg->block_len & SPRD_DMA_BLK_LEN_MASK; + + hw->trsc_len = slave_cfg->transcation_len & SPRD_DMA_TRSC_LEN_MASK; + + hw->trsf_step = (slave_cfg->dst_step & SPRD_DMA_TRSF_STEP_MASK) << + SPRD_DMA_DEST_TRSF_STEP_OFFSET | + (slave_cfg->src_step & SPRD_DMA_TRSF_STEP_MASK) << + SPRD_DMA_SRC_TRSF_STEP_OFFSET; + + hw->frg_step = 0; + hw->src_blk_step = 0; + hw->des_blk_step = 0; + return 0; +} + static struct dma_async_tx_descriptor * sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) @@ -606,6 +753,72 @@ static void sprd_dma_issue_pending(struct dma_chan *chan) return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); } +static struct dma_async_tx_descriptor * +sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_config *slave_cfg = &schan->slave_cfg; + struct sprd_dma_desc *sdesc; + struct scatterlist *sg; + int ret, i; + + /* TODO: now we only support one sg for each DMA configuration. */ + if (!is_slave_direction(dir) || sglen > 1) + return NULL; + + sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); + if (!sdesc) + return NULL; + + for_each_sg(sgl, sg, sglen, i) { + if (dir == DMA_MEM_TO_DEV) { + slave_cfg->src_addr = sg_dma_address(sg); + slave_cfg->dst_addr = slave_cfg->cfg.dst_addr; + slave_cfg->src_step = + sprd_dma_get_step(slave_cfg->cfg.src_addr_width); + slave_cfg->dst_step = SPRD_DMA_NONE_STEP; + } else { + slave_cfg->src_addr = slave_cfg->cfg.src_addr; + slave_cfg->dst_addr = sg_dma_address(sg); + slave_cfg->src_step = SPRD_DMA_NONE_STEP; + slave_cfg->dst_step = + sprd_dma_get_step(slave_cfg->cfg.dst_addr_width); + } + + slave_cfg->block_len = sg_dma_len(sg); + slave_cfg->transcation_len = sg_dma_len(sg); + } + + slave_cfg->req_mode = + (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK; + slave_cfg->int_mode = flags & SPRD_DMA_INT_MASK; + + ret = sprd_dma_config(chan, sdesc, slave_cfg); + if (ret) { + kfree(sdesc); + return NULL; + } + + return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); +} + +static int sprd_dma_slave_config(struct dma_chan *chan, + struct dma_slave_config *config) +{ + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_config *slave_cfg = &schan->slave_cfg; + + if (!is_slave_direction(config->direction)) + return -EINVAL; + + memset(slave_cfg, 0, sizeof(*slave_cfg)); + memcpy(&slave_cfg->cfg, config, sizeof(*config)); + + return 0; +} + static int sprd_dma_pause(struct dma_chan *chan) { struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); @@ -733,6 +946,8 @@ static int sprd_dma_probe(struct platform_device *pdev) sdev->dma_dev.device_tx_status = sprd_dma_tx_status; sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending; sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy; + sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg; + sdev->dma_dev.device_config = sprd_dma_slave_config; sdev->dma_dev.device_pause = sprd_dma_pause; sdev->dma_dev.device_resume = sprd_dma_resume; sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all; diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h index c545162..b0115e3 100644 --- a/include/linux/dma/sprd-dma.h +++ b/include/linux/dma/sprd-dma.h @@ -3,6 +3,10 @@ #ifndef _SPRD_DMA_H_ #define _SPRD_DMA_H_ +#define SPRD_DMA_REQ_SHIFT 16 +#define SPRD_DMA_FLAGS(req_mode, int_type) \ + ((req_mode) << SPRD_DMA_REQ_SHIFT | (int_type)) + /* * enum sprd_dma_req_mode: define the DMA request mode * @SPRD_DMA_FRAG_REQ: fragment request mode