From patchwork Wed May 3 09:56:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 98483 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp217077qgd; Wed, 3 May 2017 02:58:20 -0700 (PDT) X-Received: by 10.99.225.83 with SMTP id h19mr38582290pgk.38.1493805500273; Wed, 03 May 2017 02:58:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e64si20428390pgc.32.2017.05.03.02.58.20; Wed, 03 May 2017 02:58:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753548AbdECJ6F (ORCPT + 25 others); Wed, 3 May 2017 05:58:05 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33855 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752989AbdECJ47 (ORCPT ); Wed, 3 May 2017 05:56:59 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id 2E8E126B01C From: Guillaume Tucker To: Rob Herring , Mark Rutland , =?utf-8?q?Heiko_St=C3=BCbner?= , Neil Armstrong Cc: Sjoerd Simons , Enric Balletbo i Serra , John Reitan , Wookey , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Tucker Subject: [PATCH v5 2/5] ARM: dts: rockchip: add ARM Mali GPU node for rk3288 Date: Wed, 3 May 2017 10:56:26 +0100 Message-Id: <4b93ea388fa72c6dda0bf954104e99bcd1925267.1493804968.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Tested-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker --- arch/arm/boot/dts/rk3288.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index df8a0dbe9d91..35969041eae2 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1117,6 +1118,48 @@ }; }; + gpu: mali@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + qos_gpu_r: qos@ffaa0000 { compatible = "syscon"; reg = <0xffaa0000 0x20>;