From patchwork Fri Dec 20 14:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182280 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp607479ilf; Fri, 20 Dec 2019 06:32:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwZHOUC5jCUhVNOTAIVuoRiKbyZ3CBcnv84EfhBmeDpumTlte6NgEMoy7KioAasRgXeA7xm X-Received: by 2002:a9d:4706:: with SMTP id a6mr14158821otf.331.1576852323654; Fri, 20 Dec 2019 06:32:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852323; cv=none; d=google.com; s=arc-20160816; b=izDWx4Wslqji2P0pdAUVMup9BRoAaRTEtihKn2xPLBfoSwU/wopZHFn00C+TtT+8y1 HAxRtk3OfbuUil2mJPtMmxD6hj8lWtm7D8H25sodHzMEZcnYGAGvMtbvoQhLfDaWWZlz a6I/rym+lIyPcTTczhRJLQyPp5FRzixg1YPjSOt/EfavRQu2dQmrZtvo4wy5wQNnPtiU l4r6Wp6tyX1IdudeZqN01MNrLKPZowecmyU2WaN2/Dt6hxl3RQlxS2XFfOXnoHuFx0bi 62bjhrD9qJDiczVedSU353dVKfl6CbLZjWcHpoaSe/tWvikntW4p0Ti3mo44HJ5M2ygf mtVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=EFxXNdRXys1JcqCgsENOUtZggHQO69hlwPH2tF6F4pY=; b=sZlu3+iSUa6TKyZl16kzmMQHqrjaAvRHvMVTSn7OD9C7wXlGxJpMTnyICXw6ddNzM7 YRZ3uDO+wwIDEMC5u2XYS1aEXELGt/i8j9ylK8cjIgnuAUh65oIFMW5E/LGK0iSelLgx M3GjGUx5RbwoIJyv9PZ/cosfxtiIqoQtgr3pbwUcb63waYS3ns197KW7KuNBe80KpzDn CIjhlNouDksWC4KzqsmaeSfxIk98TFTlFGnPwXtTQ4XPaaPuuien0DeJOzNttrRXMKiJ PbKSFxgFuQBvx4QZIoF9THVR1kq+4gw4SaUFtpltYm33sGkzDl/g5zMQ59JWds4xz7kW fZZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.31.58; Fri, 20 Dec 2019 06:32:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727797AbfLTOai (ORCPT + 27 others); Fri, 20 Dec 2019 09:30:38 -0500 Received: from foss.arm.com ([217.140.110.172]:51180 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CAC431B; Fri, 20 Dec 2019 06:30:34 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B39603F718; Fri, 20 Dec 2019 06:30:32 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 01/18] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Date: Fri, 20 Dec 2019 14:30:08 +0000 Message-Id: <20191220143025.33853-2-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla It's not entirely clear for the binding document that the only way to express ARM SPE affined to a subset of CPUs on a heterogeneous systems is through the use of PPI partitions available in the interrupt controller bindings. Let's make it clear. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt index 93372f2a7df9..4f4815800f6e 100644 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer. "arm,statistical-profiling-extension-v1" - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. + SPE is only supported on a subset of the CPUs, a PPI partition + described in the arm,gic-v3 binding must be used to describe + the set of CPUs this interrupt is affine to. ** Example: