From patchwork Wed Dec 11 12:46:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181203 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp481330ile; Wed, 11 Dec 2019 04:45:30 -0800 (PST) X-Google-Smtp-Source: APXvYqxTLuTQTeca+4JMdY0ujZuWxwa0wjl5ThT3Cx3WckwEO7FF7CgLIpZfN0gVLCadQUCLrsId X-Received: by 2002:a9d:7495:: with SMTP id t21mr2149689otk.86.1576068330398; Wed, 11 Dec 2019 04:45:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576068330; cv=none; d=google.com; s=arc-20160816; b=olhyLF9CguICGsUEsaCtXiTuALd+gRHYDZq5GRZc7oHefz+lhu51FW4SotPdc+nGTd WGra2Pv5FcB8Od7X9rkwtw0xlXsefBw/6VjVHbpscnpAMSYmE5y3QG/0ovTLy7+5WKtV 8fydLByUa2ZYJh33Zx7xtV4W54pTQknlVstNpGjjWhFdp4vJeFvhnUVyovMSgiX5w2zs afw16VhQcSjibJsuMqUZVBPhOZiry9cCssTs9JVke0CTO20yIIIrbbAx3df+KPu7yKXF FqcuRMForU2mZEiuEi6wgQKxNWDaE2YRw5tLQhsDz7DITTnJA0a2MXY/v0ld8OeB7fG1 O3WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2tvalbS51NRH72d/eck6wNFaarOFGq+9ECr88otyLfI=; b=EitPWi3G1XlViS7RvKyApLu++rLao6oYWr2Hn3BVhKWm6o6lp+nJRWDGk8DbuW7ful 8jPlsel8GO2aJm7ZfSoFvC1CgkV1W6FF7sz5T2o5NtYZw+xIMS2YBTj/p++2oeHt0ELO Jvv54cZVpmvQYzyyKu+HXgYzlnFtoojPktOkwleTGT+aqN/2mLFc6lA3iLzhuvu2g/7d TEDSEBib84Jz0Do4pBnKfwaV6Xvl7r0f8GrVMaxUVYTMQ+aQi3VrU4FeX8O3muXdy3M4 pDZ4O0WQ2fKnwNesSJFyvaaCjAlQ1jd9xjwwMQFtrgysKrieS4wdKbZPWI0xUiiLmOFl /jJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oJoyfKk6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p22si973548ota.43.2019.12.11.04.45.29; Wed, 11 Dec 2019 04:45:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oJoyfKk6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729358AbfLKMpY (ORCPT + 27 others); Wed, 11 Dec 2019 07:45:24 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:42480 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729318AbfLKMpU (ORCPT ); Wed, 11 Dec 2019 07:45:20 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBBCj8sH012121; Wed, 11 Dec 2019 06:45:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576068308; bh=2tvalbS51NRH72d/eck6wNFaarOFGq+9ECr88otyLfI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oJoyfKk6hUmwxuhwQ/RokizqaBg9NBAcGl9+qwYGDaqe1sSsGOrG+WiciI9ONFbkr Bz3gEngOMeo5KhbEQHQaHxgjShp/7vSFd8AzunP9rgSEWgmM1rohvLM8LCO65FGwKS FSKTy0WdR71YZY7bjeOxjSpB7tGSewdOJDlBQUWI= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBBCj8RM105562; Wed, 11 Dec 2019 06:45:08 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 11 Dec 2019 06:45:08 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 11 Dec 2019 06:45:08 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBBCirfk125451; Wed, 11 Dec 2019 06:45:05 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Gustavo Pimentel CC: Murali Karicheri , Jingoo Han , Kishon Vijay Abraham I , , , , Xiaowei Bao Subject: [PATCH 3/4] PCI: keystone: Allow AM654 PCIe Endpoint to raise MSIX interrupt Date: Wed, 11 Dec 2019 18:16:07 +0530 Message-ID: <20191211124608.887-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191211124608.887-1-kishon@ti.com> References: <20191211124608.887-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AM654 PCIe EP controller has MSIX capability register and has the ability to raise MSIX interrupt. Add support in pci-keystone.c for PCIe endpoint controller in AM654 to raise MSIX interrupts. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index af677254a072..dbe31589eb61 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -959,6 +959,9 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, case PCI_EPC_IRQ_MSI: dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); break; + case PCI_EPC_IRQ_MSIX: + dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); + break; default: dev_err(pci->dev, "UNKNOWN IRQ type\n"); return -EINVAL; @@ -970,7 +973,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, static const struct pci_epc_features ks_pcie_am654_epc_features = { .linkup_notifier = false, .msi_capable = true, - .msix_capable = false, + .msix_capable = true, .reserved_bar = 1 << BAR_0 | 1 << BAR_1, .bar_fixed_64bit = 1 << BAR_0, .bar_fixed_size[2] = SZ_1M,