From patchwork Fri Dec 6 16:45:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 180927 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp1028855ile; Fri, 6 Dec 2019 08:47:30 -0800 (PST) X-Google-Smtp-Source: APXvYqyLuUzoZEHAUDJANaqxDafiwSQI1XAAQeouivnwxCPUlJIdGOiEpbNzW9kZjkiq22/Tld16 X-Received: by 2002:a05:6830:1f4d:: with SMTP id u13mr12393067oth.77.1575650850248; Fri, 06 Dec 2019 08:47:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575650850; cv=none; d=google.com; s=arc-20160816; b=D5BuTQP+JhS+UDlC26dgTzBeH1AmqqeR9BMeTE4py2dq5LXmbuzGjAOqd37dC/LocX dxZ1O60hdFXbzpHbCDCYLPOGe7gCPksZm2NAUoU/cFeCrWeXDO2GitO6t5kvZQ9DAHY3 l6PuZwnFbq86M5jM8FZbMoZxOGvDz3u7LJU7InOY2mPdD8qya1lonmJk3XDUbWExjskJ 9WwkzTs18f1jN+NywdqfJeIg7pdSwxYBzXjoDhTDIJOU6Jw0SmvF7uy9Q7aA5MkKIMem zXbY7oi/zi4Y/RgOTQxElDph4Pxg78YnE0y5+DTCUSYV/Mv9ELPuF1AEzgWSPzdUmiG6 KNPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YM3VwWjblZ+96a50E5Kk0PHMfn6mkHDwsOR8RbqQotE=; b=amshlAuDOD1l2E/T5UXLb521kZ0YreKvGHSx2tseWDbfKWrgUw+DgxGCg/hlpSe22H 0ingK/9y78EDcTtvCYkqZ9kJSrvYGj1szlkyVXeixIYVpXv7SrXcTKlDVf0u+v/juQvj Z23VNrP9k2ZFfeUmkZcGj9HXMlH8uJI4SV7JY+kROKQMcYprQro7cjf1HQkIYC5VIz71 LvIAEr9i6OWiDFrv5dZ14EtdSZqA4wKCpiyc2uQdlSZrssVHlE6kxVhtyLPhgJ1ThZXW FBzp+ulI44f/gujhsAEln/7gX6dhQAtKVDPX84ifamB/FwWIaqJgonXw/oKDqmi4pv1f IHKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CnFFcQlC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g2si7329130otn.117.2019.12.06.08.47.30; Fri, 06 Dec 2019 08:47:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CnFFcQlC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726513AbfLFQr2 (ORCPT + 27 others); Fri, 6 Dec 2019 11:47:28 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57204 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726315AbfLFQr0 (ORCPT ); Fri, 6 Dec 2019 11:47:26 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB6GlMio016593; Fri, 6 Dec 2019 10:47:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575650842; bh=YM3VwWjblZ+96a50E5Kk0PHMfn6mkHDwsOR8RbqQotE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CnFFcQlCv2DuqyT7CPjsraExT648eCgs8MnYMK9qN3UGo6GTIdfkwK9NiPFLnqfCa Cd7mVwjBSQVIxZCvUXXI4YmRFVfDBXOEMH+L0djc7HRlvJjcJkVsSuXSz5O92dfL4P K/cwRPiNuuRTRWVt480X1N/F5anyjNboA0USxqQI= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB6GlMf6046460 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Dec 2019 10:47:22 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 6 Dec 2019 10:47:21 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 6 Dec 2019 10:47:21 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB6GlLF6062776; Fri, 6 Dec 2019 10:47:21 -0600 From: Dan Murphy To: , , , CC: , , , , Dan Murphy Subject: [PATCH 2/2] net: phy: dp83867: Add rx-fifo-depth and tx-fifo-depth Date: Fri, 6 Dec 2019 10:45:16 -0600 Message-ID: <20191206164516.2702-2-dmurphy@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191206164516.2702-1-dmurphy@ti.com> References: <20191206164516.2702-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This code changes the TI specific ti,fifo-depth to the common tx-fifo-depth property. The tx depth is applicable for both RGMII and SGMII modes of operation. rx-fifo-depth was added as well but this is only applicable for SGMII mode. So in summary if RGMII mode write tx fifo depth only if SGMII mode write both rx and tx fifo depths If the property is not populated in the device tree then set the value to the default values. Signed-off-by: Dan Murphy Reported-by: Adrian Bunk --- drivers/net/phy/dp83867.c | 62 +++++++++++++++++++++++++++++++-------- 1 file changed, 49 insertions(+), 13 deletions(-) -- 2.23.0 diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 1f1ecee0ee2f..93649ebc87b5 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -72,9 +72,11 @@ #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) /* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 -#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_RESERVED_MASK BIT(11) /* RGMIIDCTL bits */ @@ -103,7 +105,8 @@ enum { struct dp83867_private { u32 rx_id_delay; u32 tx_id_delay; - u32 fifo_depth; + u32 tx_fifo_depth; + u32 rx_fifo_depth; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -255,18 +258,32 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; ret = of_property_read_u32(of_node, "ti,fifo-depth", - &dp83867->fifo_depth); + &dp83867->tx_fifo_depth); if (ret) { - phydev_err(phydev, - "ti,fifo-depth property is required\n"); - return ret; + ret = of_property_read_u32(of_node, "tx-fifo-depth", + &dp83867->tx_fifo_depth); + if (ret) + dp83867->tx_fifo_depth = + DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; } - if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { - phydev_err(phydev, - "ti,fifo-depth value %u out of range\n", - dp83867->fifo_depth); + + if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { + phydev_err(phydev, "tx-fifo-depth value %u out of range\n", + dp83867->tx_fifo_depth); return -EINVAL; } + + ret = of_property_read_u32(of_node, "rx-fifo-depth", + &dp83867->rx_fifo_depth); + if (ret) + dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; + + if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { + phydev_err(phydev, "rx-fifo-depth value %u out of range\n", + dp83867->rx_fifo_depth); + return -EINVAL; + } + return 0; } #else @@ -305,12 +322,31 @@ static int dp83867_config_init(struct phy_device *phydev) phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, BIT(7)); + if (phy_interface_is_rgmii(phydev) || + phydev->interface == PHY_INTERFACE_MODE_SGMII) { + val = phy_read(phydev, MII_DP83867_PHYCTRL); + if (val < 0) + return val; + + val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; + val |= (dp83867->tx_fifo_depth << + DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; + val |= (dp83867->rx_fifo_depth << + DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); + } + + ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); + if (ret) + return ret; + } + if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) return val; - val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; - val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap.