From patchwork Mon Dec 2 18:21:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 180632 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp346390ile; Mon, 2 Dec 2019 10:22:41 -0800 (PST) X-Google-Smtp-Source: APXvYqzS7TBCe3lUUTl5U4aA284tim1dGjP0smnVQTHVKuVs4n3onMoe17Ul21X+oZ6/h5dCn8dk X-Received: by 2002:a17:906:5c0d:: with SMTP id e13mr587981ejq.82.1575310961430; Mon, 02 Dec 2019 10:22:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575310961; cv=none; d=google.com; s=arc-20160816; b=DAStevxuTh0naCtuy17AN7i4yu9e0Zuox5GTiywtrqyq0CqbSD6p8bLs13boS5lgTt V8tH/3/iJe7kKFk9Y+levuNA789jFUDgfFqJfhCZv1XgPaQrBRwZPNAvZ4RRQgn32yGW kZdxyNVFk/gJLuiLwvBWEuc1j890UwOIPTClhkbi9JGUkgWf1aJTHg+O6Hdqs6ilko3S ZVAVte4BCEVXIwSzphSynYFMcTh45ZRly0DInlzcjkUamlt5wEgrdJkptiTdc2YBU1DD yDAN56Dzola1r+5jAkfugvi9SH4ctZAf6lszqNmhaovcya7m5+X/8sF3AqGY3xrfZhl8 1U9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=jVYVJ+e58bq2vZEc/BSYZDaOn+bujl1RzX1eaPukfmI=; b=UbiUerfDr2DOqOlPt+908q454dJahIrQhK7NXrkLeMAKa9Rt9yg2j9xQWot+yHFLLW CvqXmhYCdhvFj+tgs26al4qTmYMZfbD3b+fFl/hIHjIJSJ66slnPq5AsHv+be9xYiTo9 DxKl3cGDYjPfb/qA4t+OqHRInallUwEDqk21r+Am1/Ecb+X8Pu8frxFR1lLS+gNZzc04 ENMwSs9AhyA7QER54pyWcbR1SCOkG5yQ7Spti+3B5aswRK7V8VKevI14UwTqghIsyB3i 07OnieEp+ophU0V06BM9mOp88a/N/S8vokLpCtbUUhEKc3rjdXMSE3R9FcszyxCzPtOz WGYw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id df10si175509edb.101.2019.12.02.10.22.41; Mon, 02 Dec 2019 10:22:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727972AbfLBSWT (ORCPT + 27 others); Mon, 2 Dec 2019 13:22:19 -0500 Received: from mx2.suse.de ([195.135.220.15]:35940 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727872AbfLBSWQ (ORCPT ); Mon, 2 Dec 2019 13:22:16 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 9CE78AE65; Mon, 2 Dec 2019 18:22:14 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , James Tai , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 03/14] arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon Date: Mon, 2 Dec 2019 19:21:53 +0100 Message-Id: <20191202182205.14629-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191202182205.14629-1-afaerber@suse.de> References: <20191202182205.14629-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Group the non-iso reset controller nodes into a CRT syscon mfd node. Group reset controller, watchdog and UART0 into an Isolation mfd node. Group UART1 and UART2 into a Miscellaneous syscon mfd node. Cc: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd139x.dtsi | 147 +++++++++++++++++++------------ 1 file changed, 90 insertions(+), 57 deletions(-) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index c11a505e43e2..3a571f3b7e38 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -61,70 +61,31 @@ #size-cells = <1>; ranges = <0x0 0x98000000 0x200000>; - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@50 { - compatible = "snps,dw-low-reset"; - reg = <0x50 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@7088 { - compatible = "snps,dw-low-reset"; - reg = <0x7088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@7680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x7680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@7800 { - compatible = "snps,dw-apb-uart"; - reg = <0x7800 0x400>; - reg-shift = <2>; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; }; - uart1: serial@1b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b200 0x100>; - reg-shift = <2>; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; }; - uart2: serial@1b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b400 0x100>; - reg-shift = <2>; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; }; }; @@ -140,3 +101,75 @@ }; }; }; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; +};