@@ -86,6 +86,14 @@
#reset-cells = <1>;
};
+ iso_irq_mux: interrupt-controller@7000 {
+ compatible = "realtek,rtd1295-iso-irq-mux";
+ reg = <0x7000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
iso_reset: reset-controller@7088 {
compatible = "snps,dw-low-reset";
reg = <0x7088 0x4>;
@@ -105,6 +113,8 @@
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+ interrupt-parent = <&iso_irq_mux>;
+ interrupts = <2>;
status = "disabled";
};
@@ -115,6 +125,14 @@
<0x171d8 0x4>;
};
+ misc_irq_mux: interrupt-controller@1b000 {
+ compatible = "realtek,rtd1295-misc-irq-mux";
+ reg = <0x1b000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
uart1: serial@1b200 {
compatible = "snps,dw-apb-uart";
reg = <0x1b200 0x100>;
@@ -122,6 +140,8 @@
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
+ interrupt-parent = <&misc_irq_mux>;
+ interrupts = <3>;
status = "disabled";
};
@@ -132,6 +152,8 @@
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
+ interrupt-parent = <&misc_irq_mux>;
+ interrupts = <8>;
status = "disabled";
};
};
Add iso and misc IRQ mux DT nodes to RTD129x SoC family. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber <afaerber@suse.de> --- v4 -> v5: Unchanged v3 -> v4: * Rebased onto chip-info and r-bus * Dropped schema-violating second interrupts for UART1 and UART2 v2 -> v3: * Added nodes to rtd129x.dtsi instead of rtd1295.dtsi * Adopted misc compatible string * Renamed node label from irq_mux to misc_irq_mux for clarity v1 -> v2: * Rebased arch/arm64/boot/dts/realtek/rtd129x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.16.4