From patchwork Thu Nov 21 05:02:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179894 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3085784ilf; Wed, 20 Nov 2019 21:02:25 -0800 (PST) X-Google-Smtp-Source: APXvYqwQrkeLIw0vSyzTY0KPTFp4d2/Sdc/eZpYPgDyIOhy0z+RH1g7Fjt2+jzDMOQSKIBEqVhFL X-Received: by 2002:a1c:6309:: with SMTP id x9mr7135174wmb.108.1574312544813; Wed, 20 Nov 2019 21:02:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312544; cv=none; d=google.com; s=arc-20160816; b=khyM6vBlZ5hv5O//WTIhXw416xHlxOY9IjWInM4SzFthLktkRzfjASr6vYb52Prr7Q xBEq4r3tnsVTnSdgrg3t98n86qweX2R394CKvlisVViWupOZaS42bd2IPtU2lD8pUmki fSASrJSxAK8oW147s7kUQ/3ZuGGhVyAeeoWuR9gSivg6u/nWHXJ2TuM3Iw37NOffxdS2 nuR5srbTlLqkfpdZeGD6bvpIbBKGCafB39OPq1bpsKaEdmO+ZjhC/EVZ2wdoa025nK7D Ja8hXCD9YUsgxXMuYLnSIRlFa57gmNWzmvsB2cFzohiaKbGdJcZ1XMcnvUlPT1+0y/XC hLfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=16+ZOgwkos7NogLpDdMV5GgEktU05kiJXAsR5s+wJrY=; b=X71Pnb9r3IBqMAT3Kuj+CainM4YCKi5Y5zlKLCbkilTZ/6HBx97Oqbvo1yMYCWVU86 ZRPUyIfZ2Oi+1OWDYMxAcCoOC8Nwyfmb61mF8/9TxgUAaei2JeOALXS9PoOG13Ijm4Xu ykKeArqE0cDEpyfDbu1TwZYjeq0mtx6S3h1K6laL+mIg+VKAO+vRgd8MeSxO9ZFGGdX6 XLanxGK0AmkCsKD8VV+W7iXfI/spRScn/t4DLkrkVnhB3IDiDqzMU4RzD7x8JEwurFlr xWLldIV2r3wdzxoZE4DCUXs3hoJGfA0rOfv1ePx+1vPZ/kwsSd7TyM69rqB9ECceh3DG iKVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c19si1181088edt.387.2019.11.20.21.02.24; Wed, 20 Nov 2019 21:02:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726500AbfKUFCV (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:36406 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725956AbfKUFCU (ORCPT ); Thu, 21 Nov 2019 00:02:20 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 3B77BB00A; Thu, 21 Nov 2019 05:02:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state Date: Thu, 21 Nov 2019 06:02:02 +0100 Message-Id: <20191121050208.11324-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement the .irq_get_irqchip_state callback to retrieve pending, active and masked interrupt status. Signed-off-by: Andreas Färber --- v5: New drivers/irqchip/irq-rtd1195-mux.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 0e86973aafca..2f1bcfd9d5d6 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct irq_data *data) raw_spin_unlock_irqrestore(&mux->lock, flags); } +static int rtd1195_mux_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, bool *state) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 val; + + switch (which) { + case IRQCHIP_STATE_PENDING: + /* + * UMSK_ISR provides the unmasked pending interrupts, + * except UART and I2C. + */ + val = readl_relaxed(mux->reg_umsk_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_ACTIVE: + /* + * ISR provides the masked pending interrupts, + * including UART and I2C. + */ + val = readl_relaxed(mux->reg_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_MASKED: + val = mux->info->isr_to_int_en_mask[data->hwirq]; + *state = !(mux->scpu_int_en & val); + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct irq_chip rtd1195_mux_irq_chip = { .irq_ack = rtd1195_mux_ack_irq, .irq_mask = rtd1195_mux_mask_irq, .irq_unmask = rtd1195_mux_unmask_irq, + .irq_get_irqchip_state = rtd1195_mux_get_irqchip_state, }; static int rtd1195_mux_irq_domain_map(struct irq_domain *d,