From patchwork Thu Nov 14 14:59:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 179449 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp11170039ilf; Thu, 14 Nov 2019 07:00:06 -0800 (PST) X-Google-Smtp-Source: APXvYqwPFEataDMdpR1Rqz3oNYTQT7hnhDU068ZyPFF8yzvhfI8RHzAiKQnGcTFMEJO7Lz8I6x5l X-Received: by 2002:a17:906:234e:: with SMTP id m14mr8585811eja.94.1573743606523; Thu, 14 Nov 2019 07:00:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573743606; cv=none; d=google.com; s=arc-20160816; b=usyBc53qgx2iL5rWkH2P+6VRwopaT8fJthFbv0tpfHMp1vFUqTjo8hpxtIO5r0/+xv 1ft1rLp9td//Up9CpPBAVy9Zrt48i5+Y+ZPvsRxblCHeiNv5q8LIQX9opcfeeH/ZplvL llcCsMrp1Z3g49U+4MWwhG/aBEpe4aMCGVfwIJ8liLFhndxoR8ECQT5uvbO58D6pfXP1 KRkIU8XdAYYT/QbLyxhB+TofvwALrgNl/x5WEIO8057QDIGo5n12RX7YwZ8MM1Ujc1WB bnJGE/DBxiIvxBh1V9UXHISx2ie/4F84cEk5A2Hbm47aN4yorBT5ah3Q2feRvTMIFn93 j2Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=VN9jOFV7Frwuk54WF1nfP09q1zCyX3bHMUG50K0sQtk=; b=NAk8mH+aAcfy5l4CdLFF9AEHM3zv4Hywc7SCxl/F1036D2mqkU4qxrte7Yus0zVkeo /D9uYQHiod7m5lKRPkpBBAeFrGmiUEC3Gw+rJaUJxVc1wofU2YvvZExpXZ6Th3I6s9/s y14+Qe2SFaguYDlYRn5Q+xqQeKhlJqBLDUs3CmuniK9hsDitdPK7ZHI8yuDXNQoddnTy VTHNk3FUuX/VgmLU396d4ufSPvIBU7pEsGZ7Vj5W8H39Ur5xZr0Dle2JdSk3K6EWxs/a 2CeVhzCrUZbwa/IbeP/VuQ462PZuVvE8rE1f1ERPf2tZMOLaa+w7yebyKI9q8yYXr3BL 3mKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i14si4010117edr.68.2019.11.14.07.00.06; Thu, 14 Nov 2019 07:00:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726812AbfKNPAF (ORCPT + 26 others); Thu, 14 Nov 2019 10:00:05 -0500 Received: from foss.arm.com ([217.140.110.172]:44630 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726599AbfKNPAC (ORCPT ); Thu, 14 Nov 2019 10:00:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D4107328; Thu, 14 Nov 2019 07:00:01 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B5F243F52E; Thu, 14 Nov 2019 07:00:00 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, james.morse@arm.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, suzuki.poulose@arm.com Subject: [PATCH 3/5] arm64: Workaround Cortex-A77 erratum 1542418 on boot due to kexec Date: Thu, 14 Nov 2019 14:59:16 +0000 Message-Id: <20191114145918.235339-4-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191114145918.235339-1-suzuki.poulose@arm.com> References: <20191114145918.235339-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: James Morse Kexec allows us to inherit dirty ASIDs from a previous kernel. We can't wait until the next ASID rollover to cleanup, do it early as part of the cpu-errata's enable callback. This extends __arm64_workaround_1542418_asid_rollover() to put everything back as it was. Signed-off-by: James Morse [ skip CPUs not affected, refactor cpu_enable callback ] Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/mmu_context.h | 1 + arch/arm64/kernel/cpu_errata.c | 14 ++++++++++++++ arch/arm64/mm/context.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+) -- 2.23.0 diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 3827ff4040a3..434a5c661d78 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -247,6 +247,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, void verify_cpu_asid_bits(void); void post_ttbr_update_workaround(void); +void arm64_workaround_1542418_asid_rollover(void); #endif /* !__ASSEMBLY__ */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a66d433d0113..4656157ffa36 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -12,6 +12,7 @@ #include #include #include +#include #include static bool __maybe_unused @@ -650,6 +651,18 @@ needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, return false; } +#ifdef CONFIG_ARM64_ERRATUM_1542418 +static void run_workaround_1542418_asid_rollover(const struct arm64_cpu_capabilities *c) +{ + /* + * If this CPU is affected by the erratum, run the workaround + * to protect us in case we are running on a kexec'ed kernel. + */ + if (c->matches(c, SCOPE_LOCAL_CPU)) + arm64_workaround_1542418_asid_rollover(); +} +#endif + #ifdef CONFIG_HARDEN_EL2_VECTORS static const struct midr_range arm64_harden_el2_vectors[] = { @@ -932,6 +945,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .desc = "ARM erratum 1542418", .capability = ARM64_WORKAROUND_1542418, ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), + .cpu_enable = run_workaround_1542418_asid_rollover, }, #endif { diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index ae3ee8e101d6..ad4e78bb68ed 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -129,6 +129,23 @@ static void __arm64_workaround_1542418_asid_rollover(void) */ } +void arm64_workaround_1542418_asid_rollover(void) +{ + u64 ttbr0 = read_sysreg(ttbr0_el1); + + lockdep_assert_irqs_disabled(); + + /* Mirror check_and_switch_context() */ + if (system_supports_cnp()) + cpu_set_reserved_ttbr0(); + + __arm64_workaround_1542418_asid_rollover(); + isb(); + + write_sysreg(ttbr0, ttbr0_el1); + isb(); +} + static void flush_context(void) { int i;