From patchwork Fri Nov 1 08:41:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 178265 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp165843ill; Fri, 1 Nov 2019 01:40:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqwDrwnOLfkI3URRk4488M7RB/vonBZymXK3xuur1yNPl6NkLrxBrqrdfOUmAfYHimy5KcWn X-Received: by 2002:a05:6402:891:: with SMTP id e17mr10758258edy.236.1572597650118; Fri, 01 Nov 2019 01:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572597650; cv=none; d=google.com; s=arc-20160816; b=FsLX6r/pcnDC46ELRLb/4xfo/FkL1wTEV3KbwVw6+LELi4MeqhoYiIYt23NKRFDaHA FpnuxJl3BwM6hDlFJSspRw1bKVzI9umoT92qGJx8FZTPHbjS4icKY+qjNQz5tcgmHB3P PjpUzVSVYd6QFV1SANilP6jAdEzfTS/zzDWsTUlSJ1L13QDSiJ+1epZUzDpkBVITT0Fn yoxVrkGsQ0FUQU5du+wNgALUJIxCSNITtumqUr6JG51M1Cy0PlxurOvTXQQXYgptq2Sl /GPXfOTa7iFsxTUZLFL4dLBPAM4g4Kn3EH0gg/V6O63HJRO13ocJHyKlX+VENFL0eHwD DErg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DfFRpw7GPtmxTaDqZ1grWeRPjfw/85ryCRcZj2Zxl7w=; b=HdE9sQf6WSJz+4QMiiHbFIshZ0H8XlnLRSar5GaJpeSmYXrgenazufzI1OgQ8H1Lw8 ocWvhG6YVkEPc8GxGMCJ2GRx8iqLgo6PQAKIPd+ImkG7wutTKVpp0ZaMVTTkda+tpX42 Knc7/kQz8IF/+2n1HiIoLRH/dRQJv2fyA0ReOJlzQXMulyuwdnhaRvsAEowTV9StZJK7 CeIZg66ULJ+7fb1dxz/kGJCk6YyZ2iPqqqBeWxBgn/GpyKYYY+5Ud19iUCTajfqTvkWT o0Uo/EwJ9ODvtvbGouHVGYP63q5sVZJrlspq+CKQ54iqG2AlM5WWDkF3I+0CREGM94cW a4/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=udZPvzC8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gz25si5198146ejb.81.2019.11.01.01.40.49; Fri, 01 Nov 2019 01:40:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=udZPvzC8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727428AbfKAIkr (ORCPT + 26 others); Fri, 1 Nov 2019 04:40:47 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43518 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727363AbfKAIkq (ORCPT ); Fri, 1 Nov 2019 04:40:46 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xA18eZsX021394; Fri, 1 Nov 2019 03:40:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572597635; bh=DfFRpw7GPtmxTaDqZ1grWeRPjfw/85ryCRcZj2Zxl7w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=udZPvzC8uf/jzKdS3JOY6V3CXEvH+3WjFJvfQaPi5o8tiO1ArXA5vX1IgNfnAlP6S 9kC7s8wh3fc9ZWm5v9L5hWprJ3tdRhMBTJDs2YuBN7XIgfPOX0AZE7ywFITzWoAP8+ SpNPxGDOQXg79EYv3oGYtTarnmHGRLXPJ8RhuPV8= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA18eZpc121633; Fri, 1 Nov 2019 03:40:35 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 1 Nov 2019 03:40:33 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 1 Nov 2019 03:40:20 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA18eP8a036903; Fri, 1 Nov 2019 03:40:30 -0500 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v4 01/15] bindings: soc: ti: add documentation for k3 ringacc Date: Fri, 1 Nov 2019 10:41:21 +0200 Message-ID: <20191101084135.14811-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191101084135.14811-1-peter.ujfalusi@ti.com> References: <20191101084135.14811-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..86954cf4fa99 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@ { + ... + ti,ringacc = <&ringacc>; + ... +}