From patchwork Mon Oct 21 16:34:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 177124 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3647112ill; Mon, 21 Oct 2019 09:35:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqxOw6J9yG2+2jxLhfMGAqJ3ootKm/Ow9b+5yDAutLmyUgLRkMkwC6yF2+ijy4kePwRYXKb/ X-Received: by 2002:a05:6402:b38:: with SMTP id bo24mr26700622edb.103.1571675729521; Mon, 21 Oct 2019 09:35:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571675729; cv=none; d=google.com; s=arc-20160816; b=TR89SmHkJf7rtsUqunGE4aUVOrPa06FVkni/VfRWYNoo4nEz8M22kkvHJiDeL07bo2 bPhx4o6goDI3h3K+gLASjQC2M4vt0988bxYzncLTs+hzl49Gi/ZgR5FVnXeXgdUoBULu RdzbYlMeJ2gYRMboyxj73WXxrusFknRQ9ctpAURxi7kmn+VGcTHjLwTvfM36AZJKr+nD 2ROLjWm5/lYIXcfXF1q5jA6Uqi4PPnBv0pLev2QogEUJaAwQDJm5vA6v/rFD8udGTwUX XdGYyEhaDyckU6yczQi2B+onO+a++NfRfmKqoii1KVkrjwlKRfx4Bzh3NVRf9D6o1S6w 7vrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Z6+JGaqivZiMaVa2PWmZQKNNL7oxgb6eJ+drBRGH/ps=; b=cosT2zZ7xNTfA372JWhruxRmQpJvtatEjT2YiYBUX3Wl+mnAdYUUhQbMdqcvj0b3e0 lGSetdedXqy1ooJBHj/2V8kS+g/BXuNxh9g5RIZAAfjMSlUUDGdgtZOukplH9DOypJ42 ZuNuyexTJZahW2qTo1i81BgtgwniHrGhcZMhGf7aiyFXz5jnWIJGhT224zEz6gDzQRa1 rnRSeKxfuoXz1qPuOiXYC4fZFdkMZuuOn41yn/SzdLd+oYLE1GkRgC2ULOXESa5jcBbu tyfuUBblGPopmspgLGMj32JcIWZFJ7l2/AgdlStiw2MePd1mG919GrMye+KRAVRRn5Ej 7+dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ks17si1460281ejb.210.2019.10.21.09.35.28; Mon, 21 Oct 2019 09:35:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729836AbfJUQfY (ORCPT + 26 others); Mon, 21 Oct 2019 12:35:24 -0400 Received: from [217.140.110.172] ([217.140.110.172]:57656 "EHLO foss.arm.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1729739AbfJUQfX (ORCPT ); Mon, 21 Oct 2019 12:35:23 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 67D8B15A1; Mon, 21 Oct 2019 09:34:50 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2FA363F71F; Mon, 21 Oct 2019 09:34:48 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: amit.kachhap@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, deller@gmx.de, duwe@suse.de, james.morse@arm.com, jeyu@kernel.org, jpoimboe@redhat.com, jthierry@redhat.com, mark.rutland@arm.com, mingo@redhat.com, peterz@infradead.org, rostedt@goodmis.org, svens@stackframe.org, takahiro.akashi@linaro.org, will@kernel.org Subject: [PATCH 5/8] arm64: insn: add encoder for MOV (register) Date: Mon, 21 Oct 2019 17:34:23 +0100 Message-Id: <20191021163426.9408-6-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191021163426.9408-1-mark.rutland@arm.com> References: <20191021163426.9408-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For FTRACE_WITH_REGS, we're going to want to generate a MOV (register) instruction as part of the callsite intialization. As MOV (register) is an alias for ORR (shifted register), we can generate this with aarch64_insn_gen_logical_shifted_reg(), but it's somewhat verbose and difficult to read in-context. Add a aarch64_insn_gen_move_reg() wrapper for this case so that we can write callers in a more straightforward way. Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/insn.h | 3 +++ arch/arm64/kernel/insn.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 39e7780bedd6..bb313dde58a4 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -440,6 +440,9 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, int shift, enum aarch64_insn_variant variant, enum aarch64_insn_logic_type type); +u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_variant variant); u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, enum aarch64_insn_variant variant, enum aarch64_insn_register Rn, diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index d801a7094076..513b29c3e735 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -1268,6 +1268,19 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift); } +/* + * MOV (register) is architecturally an alias of ORR (shifted register) where + * MOV <*d>, <*m> is equivalent to ORR <*d>, <*ZR>, <*m> + */ +u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_variant variant) +{ + return aarch64_insn_gen_logical_shifted_reg(dst, AARCH64_INSN_REG_ZR, + src, 0, variant, + AARCH64_INSN_LOGIC_ORR); +} + u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr, enum aarch64_insn_register reg, enum aarch64_insn_adr_type type)