From patchwork Sun Oct 20 04:08:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 176984 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp1692869ill; Sat, 19 Oct 2019 21:08:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqxCXaRNQoFlXJ8poCGNwqMpOH/7bsRiDJCS6wms25h/9sGofYq1T85xpSUzpowPC5hy2cN8 X-Received: by 2002:a17:906:90d8:: with SMTP id v24mr16244765ejw.60.1571544515001; Sat, 19 Oct 2019 21:08:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571544514; cv=none; d=google.com; s=arc-20160816; b=mmWwjMjhUhi4J541DH8aS1vffSA5cnkO1uQAbvvbjTcGjguRgj/tWAsD2EdM26d9mH JQqv3xxfPMB7qMZerVHmIEXjx7lBVFxI6ihnGme91yhY/3LlF/yPQdNcVZTCFbW08KT1 i+u0xer0tVyAS9lehHmHIftbXWs1jc+Qby2wv9pX6x8mnFbSh9ioDsZfCnJA722n904D qzJPORCSxWsAsLliUnu33Aj1A6DrC9x1v0F3+jKnbGB7nwaXRAO+9wkLS2EnTRN/h7D5 rvmi06StMqrqMqKYPTz9f7/R2E3axJp3gQRnCwy++TnKoWhOo17ThXP8DdI54HX/QRhw 4i/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZY+ly5S+tw5cAkBaYYY/b09lWyZxenINjPelfFj/Zm0=; b=ERh+nce9HspIWAgx259YKCZiA6tRnQDJVsRGDwgMDJ0FEzlqLGS/3tPc6Scju7LIna hD/ZXKawgWiWxJRq9AI9rIXyI21JxeixENFozg93Qm35yK2pA2OW4Vd4aztpydnPch0I WgpaCpe7KOCJFgJovp0dfkzaRyxmYZpwd1zEUPKmrdPtpf4HtZJCWGpGdupx6GK1xEh/ +TopckMEc6JDPPFLswkHAnKEfoV+vcy8JcwlK+5zCSA8bgFnK6X82PEZFh+KwjZFqWhn 4s0uq/U7mooCPN8xtTrRkynM2W8wVRFmI6YVA5+D7wTDmI6zOMbjoFOIcXYBQwPJWZOo Od0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ok21si6221776ejb.95.2019.10.19.21.08.34; Sat, 19 Oct 2019 21:08:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726390AbfJTEIc (ORCPT + 26 others); Sun, 20 Oct 2019 00:08:32 -0400 Received: from mx2.suse.de ([195.135.220.15]:37166 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725851AbfJTEIb (ORCPT ); Sun, 20 Oct 2019 00:08:31 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 839B3B3E5; Sun, 20 Oct 2019 04:08:29 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , info@synology.com, Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: realtek: Add RTD1296 and Synology DS418 Date: Sun, 20 Oct 2019 06:08:17 +0200 Message-Id: <20191020040817.16882-9-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191020040817.16882-1-afaerber@suse.de> References: <20191020040817.16882-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Device Trees for RTD1296 SoC and Synology DiskStation DS418. Cc: info@synology.com Signed-off-by: Andreas Färber --- v1 -> v2: * Moved SPDX-License-Identifier to top * Dropped "arm,armv8" (Rob) * Changed from MIT to BSD-2-Clause (Rob) * Dropped accidental enable-method and cpu-release-addr * Fixed DS418 to use rtd1296.dtsi arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1296-ds418.dts | 30 +++++++++++++ arch/arm64/boot/dts/realtek/rtd1296.dtsi | 65 +++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1296-ds418.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1296.dtsi -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index e7ff40461ddc..555638ada721 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -5,3 +5,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts b/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts new file mode 100644 index 000000000000..5a051a52bf88 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1296.dtsi" + +/ { + compatible = "synology,ds418", "realtek,rtd1296"; + model = "Synology DiskStation DS418"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi new file mode 100644 index 000000000000..0f9e59cac086 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1296 SoC + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include "rtd129x.dtsi" + +/ { + compatible = "realtek,rtd1296"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +};