From patchwork Thu Oct 3 11:12:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 175077 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp155262ill; Thu, 3 Oct 2019 04:12:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+MavksE16BO9zDOjyNm0c/h9/sH84Tfy0RNvsaf/Pzv9AGwH8nFt9X9SXuqmUbujRsszD X-Received: by 2002:aa7:c4d0:: with SMTP id p16mr8870220edr.266.1570101146470; Thu, 03 Oct 2019 04:12:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570101146; cv=none; d=google.com; s=arc-20160816; b=Z45joboVcYNbkq0Y8DC7gUy5hDmGMOIgXzyeBCL5Dj5k3xjfu3l8iSMqrnwxLn7xY+ yMk+ODcZNOtcqIaZPZceoVniOv1LUeHkGb9/e3i5raI0ovwv99M00lkuOhL/6ohS9W2B u5Tx5dGS9XcEPKYCkG8WsSg0D75ll9WQR+JxAfKB9gFH7gzp3dnl/XnQ2z9cZya2MW8c l5jfSIouKSq9aGYfVCqom62mSr2axXkghzqIllgLbDiC8LBSjZHT35qrdj/a9WkP6acn 6ZH9Btmo3BzZryE/h+hcIUesZW6eYh+bgUcH8gnfPCe0vNN43Y+TgK8e8IyfLm6hacE6 Tung== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=k3f1GWKngUCmrZsmnDB5aCzxdbreBHrseUS3Mhc6gYw=; b=GXIIM61MbUYOPthtcT7EUaZlonFmRrgjigOZKfR4LpUc5B+LtgStuC7Or8tJfD2CQh Wzd8QGyzq5bhrt/Kue/OwtStE2aWW8Vgecw52LHp0pEi5yxtgpFg+hdA2YoqoM4Kq7QQ dRrnvXXZRSdIUXIExsHxLt4deYTaaStYMqjtGQfF3G9F0he8wBo1uoey/8OaewfT3d1C GiPzQ2MeaxM89BBel5lAZ0g8HpuYnHa4WiUTJYiKGa3HXGbla8X+O3ot67slliAmxIbe /ZgKNcMgQsbvtRINgg0vW56tlnxb0whK/+UCOlKaH4rxYlWFVjb2zs7JzsobWY/5oQma L6iA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d24si1290455ede.119.2019.10.03.04.12.26; Thu, 03 Oct 2019 04:12:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729927AbfJCLMW (ORCPT + 27 others); Thu, 3 Oct 2019 07:12:22 -0400 Received: from foss.arm.com ([217.140.110.172]:41780 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728140AbfJCLMT (ORCPT ); Thu, 3 Oct 2019 07:12:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3E251597; Thu, 3 Oct 2019 04:12:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D3C843F706; Thu, 3 Oct 2019 04:12:17 -0700 (PDT) From: Julien Grall To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, catalin.marinas@arm.com, suzuki.poulose@arm.com, Julien Grall , Jonathan Corbet , linux-doc@vger.kernel.org Subject: [PATCH 2/4] docs/arm64: elf_hwcaps: sort the HWCAP{, 2} documentation by ascending value Date: Thu, 3 Oct 2019 12:12:09 +0100 Message-Id: <20191003111211.483-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191003111211.483-1-julien.grall@arm.com> References: <20191003111211.483-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Part of the hardware capabilities documented in elf_hwcap.rst are ordered following the definition in the header arch/arm64/include/uapi/asm/hwcap.h but others seems to be documented in random order. To make easier to match against the definition in the header, they are now sorted in the same order as they are defined in header. I.e., HWCAP first by ascending value, and then HWCAP2 in the similar fashion. Signed-off-by: Julien Grall --- Documentation/arm64/elf_hwcaps.rst | 64 +++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 32 deletions(-) -- 2.11.0 diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 91f79529c58c..9ee7f8ff1fae 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -119,10 +119,6 @@ HWCAP_LRCPC HWCAP_DCPOP Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001. -HWCAP2_DCPODP - - Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. - HWCAP_SHA3 Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001. @@ -141,30 +137,6 @@ HWCAP_SHA512 HWCAP_SVE Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. -HWCAP2_SVE2 - - Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. - -HWCAP2_SVEAES - - Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. - -HWCAP2_SVEPMULL - - Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. - -HWCAP2_SVEBITPERM - - Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. - -HWCAP2_SVESHA3 - - Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. - -HWCAP2_SVESM4 - - Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. - HWCAP_ASIMDFHM Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. @@ -180,10 +152,6 @@ HWCAP_ILRCPC HWCAP_FLAGM Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001. -HWCAP2_FLAGM2 - - Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. - HWCAP_SSBS Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. @@ -197,6 +165,38 @@ HWCAP_PACG ID_AA64ISAR1_EL1.GPI == 0b0001, as described by Documentation/arm64/pointer-authentication.rst. +HWCAP2_DCPODP + + Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. + +HWCAP2_SVE2 + + Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. + +HWCAP2_SVEAES + + Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. + +HWCAP2_SVEPMULL + + Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. + +HWCAP2_SVEBITPERM + + Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. + +HWCAP2_SVESHA3 + + Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. + +HWCAP2_SVESM4 + + Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. + +HWCAP2_FLAGM2 + + Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. + HWCAP2_FRINT Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.