From patchwork Thu Oct 3 11:12:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 175075 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp155183ill; Thu, 3 Oct 2019 04:12:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqy5ex3wK3KJzCCvJxwMNebWMFQuxVgLRBAmbv7quEH+v1Y5ehmIzBS7LHnYheKzusKhckFE X-Received: by 2002:a17:906:7a55:: with SMTP id i21mr7180840ejo.206.1570101142772; Thu, 03 Oct 2019 04:12:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570101142; cv=none; d=google.com; s=arc-20160816; b=nhmphqxCG4VH0E2+SY05gsDoDo3/6ulhOVcxQhfGAMFOBD6z67jxFKc0+FTH1DfbED O2Vq6ZCsBA/v+rfN9naYRRx5+z+Q6pb3SCMXBdhPqpEpRKPWTMAModinEqRN9UHmu4Ag l//KqiNIwNWlGehjicE29aQnUk3vQUC7WvC3sc70/upLkVq2Ubh1egMxj5GGVRzD4WZz 4iWH+mrFe7hsUybgIXt8bL7IGYRa1PaXxzheFjPSnIO34p1e8PJsfUkV2hwG2S3ZdlZA XJBZUZ47DH0wrdXrFnh7f4wDQknmSjcsIxWQdE+J+XJ9XzvQ2GKLtLo6QCBv+B2XVebv Z/Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=66dgkOuNY0ICUET5jcY++oZdCP0XpOMYe+qHYcAil7g=; b=PtNEwpQgdKYev6t2IT5hhM5z4gnZJDMBzXK2P0DCk3FiD8B+5bx7tvoatjZqlzLk7g P4C5YrfNuqL/qb+RxV5vWIvMx6MTRWn7DkmOnhOT01AqdHWcIAlkH/m5SdueuCWWKikk RXYUruMAwb1svbh5iVeSBaNxekxOnf74WVDFyLdcYh7Wxx6465HP3ayy2JxDvMoaNXPm NT/gM5+1282kaFDND/EPtwqAEqBdBr0khZ7+tOsj+VTCL5idFLVb7HdLWfzff/TBp8mz Y6adj7QXCi77dRBMA67209d3DKacVd6Pp5+a7KL8XRWitmEDj9XemSj7g917UJOez9O4 sbwg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d24si1290455ede.119.2019.10.03.04.12.22; Thu, 03 Oct 2019 04:12:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729895AbfJCLMT (ORCPT + 27 others); Thu, 3 Oct 2019 07:12:19 -0400 Received: from foss.arm.com ([217.140.110.172]:41770 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728140AbfJCLMS (ORCPT ); Thu, 3 Oct 2019 07:12:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E7EA1576; Thu, 3 Oct 2019 04:12:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B2563F706; Thu, 3 Oct 2019 04:12:16 -0700 (PDT) From: Julien Grall To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, catalin.marinas@arm.com, suzuki.poulose@arm.com, Julien Grall , mark.brown@arm.com Subject: [PATCH 1/4] arm64: cpufeature: Effectively expose FRINT capability to userspace Date: Thu, 3 Oct 2019 12:12:08 +0100 Message-Id: <20191003111211.483-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191003111211.483-1-julien.grall@arm.com> References: <20191003111211.483-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The HWCAP framework will detect a new capability based on the sanitized version of the ID registers. Sanitization is based on a whitelist, so any field not described will end up to be zeroed. At the moment, ID_AA64ISAR1_EL1.FRINTTS is not described in ftr_id_aa64isar1. This means the field will be zeroed and therefore the userspace will not be able to see the HWCAP even if the hardware supports the feature. This can be fixed by describing the field in ftr_id_aa64isar1. Fixes: ca9503fc9e98 ("arm64: Expose FRINT capabilities to userspace") Signed-off-by: Julien Grall Cc: mark.brown@arm.com --- arch/arm64/kernel/cpufeature.c | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9323bcc40a58..cabebf1a7976 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -136,6 +136,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),