From patchwork Tue Oct 1 06:17:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174819 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp8116528ill; Mon, 30 Sep 2019 23:17:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqy7mqoVALsl8tdmMXj76GUpEL32XRzLh/FA1jh/FqRDNHyuJ+Yg1XsBAmFoOOQk5RCNzu3N X-Received: by 2002:a17:906:3110:: with SMTP id 16mr22406702ejx.306.1569910639273; Mon, 30 Sep 2019 23:17:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569910639; cv=none; d=google.com; s=arc-20160816; b=WABY/WMkDXpR8QAvig+v1lYJ1K2fvMAbLlJ4AQVkrtPU5l+h0qlGA47HwRIswLwLwu /9mpz6Om1QJTfYDhMmmDwwxDSIF00zH98zDjhL9fjmYzE6EaM58QHPOWGPJna57N2tYA HjM5RlS36Xh/HZ8uM39ufGLdEUHCky8lOJqUhxx0o694i1TKGSpxAIhJmgVSjIRHhE+N QHstyG5vVA3tFG1stgijBRroAgl8Ey4DTjv8SrQqhBDD6gx6n8lEj8RbZ3gdWw4WXsmY QXFf0Npa77SmNa5E/2sjMLt6CSbViWHPuveeK+Xs+w0G9WDLrPIuwLIWISGVCl2F2Lky quBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HyIOBD3MNPmsZnPcqMBjSQyryNrZzCytNl/H3AWymMU=; b=pN7yrxiXdFXC+T5zrzhKHc9li5anV2umrd3MxccY3RJKPG/pHGckGCWfAIKpMIZONX l5qZXaTC8BMfA3Orxh/+F97h+6Sv7uWVVIZ1GnjrKdUb+l1wLQM/uEQXzzjXovM5Ul/r ZBdky9S8DsMIzAaG1EIryihl/nN2EQ9G0gILBuLqmbS7YnPwlpij5FECIHmoe9V1a7Hq TZ+e5i2j2/gHF3k+cqXArexmTSLcZYBXMwUEBx2IiFZ4u8vd4WuaG4sv/Rvl5UjlR33F ZAGjrSC7cEIKEHWtGCv/sAqKpMRmzxOiOoqZuElTg5vXay3cQoK9DI/mkvbxYh4GQTOw +kkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pP+Mg3kW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id rl13si8491195ejb.228.2019.09.30.23.17.19; Mon, 30 Sep 2019 23:17:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pP+Mg3kW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732843AbfJAGRS (ORCPT + 27 others); Tue, 1 Oct 2019 02:17:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45100 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732815AbfJAGRO (ORCPT ); Tue, 1 Oct 2019 02:17:14 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x916H8W9128340; Tue, 1 Oct 2019 01:17:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569910628; bh=HyIOBD3MNPmsZnPcqMBjSQyryNrZzCytNl/H3AWymMU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pP+Mg3kWp8QtuHUso4CLX8Ww2iZb8kHUOzpRh/IxbPKoy7MueOJ6OEXUht935DP2M H9y8aoDJ8kZd/EoZUrxu0cDwho+8AjGsYDdExx4lOLCQcA7Q1RujU/5NLXdnDZ0ZAg qIE3gS31Qe711fjxTOBXlQls7FEMNxB4JXdrJyz4= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x916H84e116057 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Oct 2019 01:17:08 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 1 Oct 2019 01:16:57 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 1 Oct 2019 01:17:07 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x916GGXI090310; Tue, 1 Oct 2019 01:17:03 -0500 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v3 13/14] dmaengine: ti: New driver for K3 UDMA - split#6: Kconfig and Makefile Date: Tue, 1 Oct 2019 09:17:03 +0300 Message-ID: <20191001061704.2399-14-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191001061704.2399-1-peter.ujfalusi@ti.com> References: <20191001061704.2399-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Split patch for review containing: Kconfig and Makefile changes DMA driver for Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P) The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P is architected to facilitate the segmentation and reassembly of SoC DMA data structure compliant packets to/from smaller data blocks that are natively compatible with the specific requirements of each connected peripheral. Multiple Tx and Rx channels are provided within the DMA which allow multiple segmentation or reassembly operations to be ongoing. The DMA controller maintains state information for each of the channels which allows packet segmentation and reassembly operations to be time division multiplexed between channels in order to share the underlying DMA hardware. An external DMA scheduler is used to control the ordering and rate at which this multiplexing occurs for Transmit operations. The ordering and rate of Receive operations is indirectly controlled by the order in which blocks are pushed into the DMA on the Rx PSI-L interface. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet / TR mode) - MEM_TO_DEV (Packet / TR mode) - Cyclic (Packet / TR mode) - Metadata for descriptors Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/Kconfig | 13 +++++++++++++ drivers/dma/ti/Makefile | 1 + 2 files changed, 14 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index d507c24fbf31..b6b7571be394 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -34,5 +34,18 @@ config DMA_OMAP Enable support for the TI sDMA (System DMA or DMA4) controller. This DMA engine is found on OMAP and DRA7xx parts. +config TI_K3_UDMA + tristate "Texas Instruments UDMA support" + depends on ARCH_K3 || COMPILE_TEST + depends on TI_SCI_PROTOCOL + depends on TI_SCI_INTA_IRQCHIP + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select TI_K3_RINGACC + default y + help + Enable support for the TI UDMA (Unified DMA) controller. This + DMA engine is used in AM65x. + config TI_DMA_CROSSBAR bool diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 113e59ec9c32..ebd4822e064e 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o +obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o