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[209.85.220.65]) by mx.google.com with SMTPS id r6sor249441pgs.80.2019.09.25.16.42.34 for (Google Transport Security); Wed, 25 Sep 2019 16:42:34 -0700 (PDT) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l1rHJE7h; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YKLbWLWjJ/GA5qz2gzrLI3oAv45tZggVEaoyYmAEWtc=; b=l1rHJE7hxxmeTFkh1J9YV8QMV1yV0qFXV/DmDWNsLVb2CYq7qYSUgzimth3Sm/WpfC YWcrIQUFR2O2toA2iR/QzLOROQiwG171rBZSbi0sjNtVqYU9zdends52ay6d2mJkaVFC FtShBLWc9mElkWRSKgv70PgTH40gn+Tc8nJi53MKUQNJZuSmlje0XLRZvVRfk85PwRL0 W3vhi922biTqSjfQTQnZD+R33u6YXHQoFZ8QthoyMdEBFMRdrQrhrzyFhUDHaSDfyRVv EP6IDGGBXKPs00w/3avZo8yti/H9cxL6e/7vcJNssTDqNu5lRTEuw3edBZQUJPxyoXYH XP2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YKLbWLWjJ/GA5qz2gzrLI3oAv45tZggVEaoyYmAEWtc=; b=VXYXmyprp/y2MP3veCcyURSzz5jeM3gTEEKRluZfUs7+w63czBXtgE2HXasD2iXgcp OkNoL0cORLO8Eo8myDgUY6vCDq4xs7CR6Xu9BMhnPBacwZMn8SXxTAS8kt3oe2dA2VZd cXWpiO2C4qLZJ29iz8EmTP+l1sgf7xfpNC+DigKhhDI5F/UJDeVMOd/M4A2xTy3iH8fU x81aSgQRSx+t57cG53XQgfMDz+OVgUkHNnl3Ig686g8vli/7PcvF3SMcJFmQ0dpFu/3K BYSL4rIdhmoy1oxYxCj9fRNI4SSnPdJiI3fOZOrUMZuBHT50fxfPvpBGFpPgZn6v/wIR b3aQ== X-Gm-Message-State: APjAAAV2Q6A3P4Dh+eUVejWI6O3nZ7TlCITtmJb6A5RH4bSbBoLfTigB pPHXi3iBaKhozThZotKdsviEqGHX X-Google-Smtp-Source: APXvYqx/aC5q8MMHMmA8YIA0gNGSPcJcNCThJHGYsY3eE0QwFH+ToKX9bx4/+M03ERzZoDMMHZ0kbg== X-Received: by 2002:a63:ff1a:: with SMTP id k26mr471666pgi.154.1569454954359; Wed, 25 Sep 2019 16:42:34 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2601:1c2:680:1319:692:26ff:feda:3a81]) by smtp.gmail.com with ESMTPSA id d1sm131127pfc.98.2019.09.25.16.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 16:42:33 -0700 (PDT) From: John Stultz To: lkml Cc: Yu Chen , Greg Kroah-Hartman , Felipe Balbi , Andy Shevchenko , Rob Herring , Mark Rutland , Matthias Brugger , Chunfeng Yun , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, John Stultz Subject: [PATCH 2/5] usb: dwc3: Execute GCTL Core Soft Reset while switch mode for Hisilicon Kirin Soc Date: Wed, 25 Sep 2019 23:42:21 +0000 Message-Id: <20190925234224.95216-3-john.stultz@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925234224.95216-1-john.stultz@linaro.org> References: <20190925234224.95216-1-john.stultz@linaro.org> From: Yu Chen A GCTL soft reset should be executed when switch mode for dwc3 core of Hisilicon Kirin Soc. Cc: Greg Kroah-Hartman Cc: Felipe Balbi Cc: Andy Shevchenko Cc: Rob Herring Cc: Mark Rutland Cc: Yu Chen Cc: Matthias Brugger Cc: Chunfeng Yun Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Yu Chen Signed-off-by: John Stultz --- drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++ drivers/usb/dwc3/core.h | 3 +++ 2 files changed, 23 insertions(+) -- 2.17.1 diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 999ce5e84d3c..440261432421 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -156,6 +169,10 @@ static void __dwc3_set_mode(struct work_struct *work) dwc3_set_prtcap(dwc, dwc->desired_dr_role); + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { @@ -1316,6 +1333,9 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 1c8b349379af..b3cb6eec3f8f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1029,6 +1029,7 @@ struct dwc3_scratchpad_array { * 2 - No de-emphasis * 3 - Reserved * @dis_metastability_quirk: set to disable metastability quirk. + * @gctl_reset_quirk: set to do a gctl soft-reset while switch operation mode. * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. */ @@ -1219,6 +1220,8 @@ struct dwc3 { unsigned dis_metastability_quirk:1; + unsigned gctl_reset_quirk:1; + u16 imod_interval; };