From patchwork Thu Sep 5 16:17:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 173157 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp935058ilq; Thu, 5 Sep 2019 09:18:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqxO886epbHoN3pKpGy2IKJ2joOtLS/PbpCLfbVWqXW/IAqk0vgH6P0l7RVEqWre2oGq3h+R X-Received: by 2002:a17:902:ba16:: with SMTP id j22mr4025540pls.253.1567700298084; Thu, 05 Sep 2019 09:18:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567700298; cv=none; d=google.com; s=arc-20160816; b=IuXQGaTvojuuKMoJvhCKgZC/31dVH6JodScyAlBwbhV3HacE/GaKL1Hd3fsTq6HJyX 5bd55ImG72krNksXTLl1AOV0tjujW08RVePDhkrmHUr+Qsszx7gz5a7Q+4sGMl2qsYOA quGP2Mzi29CBJ2hBRBIM7siOjdM7tLo3h8j28O2vXtWJdL9QSAz6VGhGBNr8uVeOLtkm RSzgkdPMzeiAujjP0u7vjgnjLzGa+fLtbyJt9uzCQThfZw6SLDsy2OH6pKebNcjWvzLY VuRiU78gR65Owdw2sVirygbDd/VLonr0h6LePbOBGM2q6XndArMzXJUa9VBZ1iMXmg51 EvZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=NoTtLr1lztWfrS92BUWnGWn3zk0jvQAYseg1lZWuSGs=; b=s0vpEh7W3c/6w24UIFIyGiw3TMGKtuVeB40a4hM5b7STTCKPLvuvs/+li7JXPfw73L 7RBKAExU90fNoj0fm+BP2IV9g2wktJ0C9ZukT5vETMhnMybGz153sHK2Ub2sJ0Ps8Bcv zVu/8y8eSaDV26ZQyA1RIhNOfaeJ0Me6oN/+8v0aoElGae3B4Owozd7/hZSVmNEHrkgJ 3EqYUWYLcQHHQtC5YCcAFx4zyXn/TMbCvwPV23GyN73NSHtKgWB9KGRM6sB2Ou/k8us9 inaIWRc+93SF1fKxAAccmKX9uEsR3wsm0ANgmGsP7bJCr9OjGhwju1ecLIGtq/u94APP Iy1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GFbERyZ9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si2375086pjn.58.2019.09.05.09.18.17; Thu, 05 Sep 2019 09:18:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GFbERyZ9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388334AbfIEQSQ (ORCPT + 28 others); Thu, 5 Sep 2019 12:18:16 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:33898 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388096AbfIEQSL (ORCPT ); Thu, 5 Sep 2019 12:18:11 -0400 Received: by mail-pf1-f195.google.com with SMTP id r12so2090696pfh.1 for ; Thu, 05 Sep 2019 09:18:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NoTtLr1lztWfrS92BUWnGWn3zk0jvQAYseg1lZWuSGs=; b=GFbERyZ9NRV2dkkLT4vQsg2O43TovjaGYNn6dZQb4zlipk1hrBEI93ONy4uCdy17BN qs6turZaX0cjL2hsvD0XQcPWWyT5eGXz7QIlN5q8rtchZ5viCWRBDwkHQ7obcrcC3Uar 1ortXnAwgQMvUwFZEFdfF67Zd3yS6nt3iV9SSsbRUiIhAZwUvGND/emO1CKYf2KWOr28 VxlM82pRtImf20eiipHbpwiiWXaq0nZI2+bBsKhiaerAHkOFKlpVyiIpgMWISCo/STX0 lWqLo+YlveCj4WJwPQ/Qdyw/LyipxCRHxudVAm/baaKD40BYKWBjg0PjlTT0keABvYme Sx5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NoTtLr1lztWfrS92BUWnGWn3zk0jvQAYseg1lZWuSGs=; b=B3oqoqbPdwNsj+1z65o4F8m1Jze6EpfoH+lMdY8nRX3T6uvkOHLVH/cWLuhAL1RbsQ rlYm+vNXz6pzaMBbYc5xaBe4YOZJtL0XPezp1uJXJc4j5D1ikC5XgXkpSN0t2yBYOG9r vFT0x78PQ3dAZQBWM7eckY5qkAvWUFQR6ptXA6C/d00bupoUkHH+Xa+0BstFLfuC8NFF gbyEBejxxyG2vz7nKKlUCbgpKeN84rjjJuFlkYyESERYAjriFNihhffGtvXkDVwDgyzP gcAN+/9WcBE2fkH591j/x6j5DewnNmmrWBwlbKkx/b2TIYFPNuO/Ols/8ey+2lDdQDD1 WMNA== X-Gm-Message-State: APjAAAXkqc11KoGbqukOx0JUhWkW6ggXU4w3++Yq7ThIJiAqjX5ysxu2 5bndtidEH5YH7wodgliDetamWw== X-Received: by 2002:a63:60a:: with SMTP id 10mr3873993pgg.381.1567700290813; Thu, 05 Sep 2019 09:18:10 -0700 (PDT) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id m129sm6324005pga.39.2019.09.05.09.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 09:18:10 -0700 (PDT) From: Mathieu Poirier To: stable@vger.kernel.org Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-omap@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [BACKPORT 4.14.y 08/18] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Date: Thu, 5 Sep 2019 10:17:49 -0600 Message-Id: <20190905161759.28036-9-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190905161759.28036-1-mathieu.poirier@linaro.org> References: <20190905161759.28036-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vignesh R commit 61dc8493bae9ba82a1c72edbc6c6065f6a94456a upstream As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this and set this flag for TI 66AK2G SoC. [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf Signed-off-by: Vignesh R Acked-by: Marek Vasut Signed-off-by: Cyrille Pitchen Signed-off-by: Mathieu Poirier --- drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index f22dd34f4f83..ff4edf4bb23c 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -38,6 +38,9 @@ #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 16 +/* Quirks */ +#define CQSPI_NEEDS_WR_DELAY BIT(0) + struct cqspi_st; struct cqspi_flash_pdata { @@ -76,6 +79,7 @@ struct cqspi_st { u32 fifo_depth; u32 fifo_width; u32 trigger_address; + u32 wr_delay; struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; @@ -623,6 +627,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + /* + * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access + * Controller programming sequence, couple of cycles of + * QSPI_REF_CLK delay is required for the above bit to + * be internally synchronized by the QSPI module. Provide 5 + * cycles of delay. + */ + if (cqspi->wr_delay) + ndelay(cqspi->wr_delay); while (remaining > 0) { size_t write_words, mod_bytes; @@ -1184,6 +1197,7 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; + unsigned long data; int ret; int irq; @@ -1241,6 +1255,10 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); + data = (unsigned long)of_device_get_match_data(dev); + if (data & CQSPI_NEEDS_WR_DELAY) + cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, + cqspi->master_ref_clk_hz); ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, pdev->name, cqspi); @@ -1312,7 +1330,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { #endif static const struct of_device_id cqspi_dt_ids[] = { - {.compatible = "cdns,qspi-nor",}, + { + .compatible = "cdns,qspi-nor", + .data = (void *)0, + }, + { + .compatible = "ti,k2g-qspi", + .data = (void *)CQSPI_NEEDS_WR_DELAY, + }, { /* end of table */ } };