From patchwork Wed Jul 10 14:10:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 168806 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp10015995ilk; Wed, 10 Jul 2019 07:10:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjH8aQ6KEwGF7I2is8edchSU46c4y/KquMPgwaT1eT50tKq9+gxzDRed+rWxsvLZ5/23Cc X-Received: by 2002:a17:902:b608:: with SMTP id b8mr39595306pls.303.1562767834260; Wed, 10 Jul 2019 07:10:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562767834; cv=none; d=google.com; s=arc-20160816; b=lFqzQ1/wSsTDWERC5xTEx+Jg91bCTfhsTiS9zIH40jlbp54XIq7+8F81Gn8N1VqzvD oO9eVN2ZgD0oi4OuCl0lUrdzaMkx+D96fyD3ECF+HRBhdDmVSRPenPY1ulWb16dDQKXN HsdoawvHXBFswl3AE8Dv8rl3H2ktM8SxIxvapE8GQFat6tlLq+xCK+3m0qP22T2rrBa2 M0nNo0Vk8vWwIPP5KiIwEJg6bOzDLer9qqzi2ItKi6DmybN0En9q9zP2sltkeC60x7el LsliOjmjwRlRITZN7Chj47EixAfF5dHq+VqkQpLiG2wvAxpks4a+iBYR6Lz18KblDbkS F+Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature; bh=oEpi+6+0w26RCxBP4UT6DzJfnAX/f9uFoVKZM8Skn8A=; b=wdzSkco6AHZ3eOs4oc0RDgywka0yxH192caeie1Ey2vagGjz5dfVEDhdEE4to9sCJK 3bfKCAg020H/TCQv4mTftyQyZ8SUbT291QARUsvf9qlyU4/tM9HPCttuwlCUTBXu7lMw l4cO1OGOVBtMEZxO7exnMLqcgKYWUpPJG+igFz2rPf43H/FVjepBDKzLdBqAnrsHzXuz 4L1EczKWmXtCZ7r05oWZHUxs/A4sjYd3pzBAGQbJoBSfTv5JaU3E7KBjvm4qC3rSgjUW NEBQ25E4YRsSdCW7z+RZ6pP99WF2dy0HVPzudHzTczW7IDtdJznjD5iXvY4WtoYnZ6TD 6wig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@aj.id.au header.s=fm3 header.b=Kz5a5tTx; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=sjRKgULh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g20si2442328pfh.95.2019.07.10.07.10.33; Wed, 10 Jul 2019 07:10:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@aj.id.au header.s=fm3 header.b=Kz5a5tTx; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=sjRKgULh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727773AbfGJOKX (ORCPT + 30 others); Wed, 10 Jul 2019 10:10:23 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:36623 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727595AbfGJOKX (ORCPT ); Wed, 10 Jul 2019 10:10:23 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DE6A3220A3; Wed, 10 Jul 2019 10:10:19 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 10 Jul 2019 10:10:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=fm3; bh=oEpi+6+0w26RCxBP4UT6DzJfnA X/f9uFoVKZM8Skn8A=; b=Kz5a5tTxNyorBcpc+UNoDcGZpcJKbJC4GIVEch3yMC Rhi3ealHNcRancfrfjCRkHgsXQBmT1B55ANVKy9S0SYuEXYdroWXy0G07sMA8BBu CNfXnuAcI29EpjBlakDLLMqJoDttEkzNecg47h2RUXU1qbU9dd8jxbmfMo8c6CCx JWv0ZjpQM9BrCMhVMUC+TOrNNlvnMI4HmRrZGmFAAvXzPpaneWpaDx+DjaOshBYJ +xeGhGESLn9jBWUshcUU4fISJVA1ndYMFre96rIbKJ1bUHoWzgQE+pPLAqV+Pcdm s4I8NUEB/03sBb3bmRYxRqSPNvwouIcf98U1twAUiSFw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :message-id:mime-version:subject:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; bh=oEpi+6+0w26RCxBP4 UT6DzJfnAX/f9uFoVKZM8Skn8A=; b=sjRKgULhpy0LQqshO1disWZtV/hBTF9wo ZlAq/FM7O7aKxYNtCcqCk4YlTvJnGeahvgjtCzKNEG9HHZYqmo7YQrpDfR87kEel cCu4WeDaL7nywSRsLUsOTMrGDmmZ7O9pOuEAw3Qfn5var7OQan+RAd5ysijMJHJX 2ljMxd/j3wTifFaNlE1OuYsNbaXSUhvuWwH/AeU8YncMNVDdFAYIl9LVCtcAD5QE We94FlOQojDdQXn54u0ZVO5FMX6EkhRqePNBPDUZ/tzquYgK+gbEu8vkmte+kF4D dFX0pYQuJyC2tUI+FMTn+3y8FdT1cDdSlJc1h2twwidxoLj3AGz5Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduvddrgeeigdejgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgggfestdekredtredttdenucfhrhhomheptehnughrvgifucfl vghffhgvrhihuceorghnughrvgifsegrjhdrihgurdgruheqnecukfhppedugedrvddrke ehrddvvdenucfrrghrrghmpehmrghilhhfrhhomheprghnughrvgifsegrjhdrihgurdgr uhenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from localhost.localdomain (ppp14-2-85-22.adl-apt-pir-bras31.tpg.internode.on.net [14.2.85.22]) by mail.messagingengine.com (Postfix) with ESMTPA id 9E52780064; Wed, 10 Jul 2019 10:10:14 -0400 (EDT) From: Andrew Jeffery To: linux-clk@vger.kernel.org Cc: Joel Stanley , mturquette@baylibre.com, sboyd@kernel.org, ryanchen.aspeed@gmail.com, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Andrew Jeffery Subject: [PATCH] clk: aspeed: Add SDIO gate Date: Wed, 10 Jul 2019 23:40:09 +0930 Message-Id: <20190710141009.20651-1-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joel Stanley The clock divisor comes with an enable bit (gate). This was not implemented as we didn't have access to SD hardware when writing the driver. Now that we can test it, add the gate as a parent to the divisor. There is no reason to expose the gate separately, so users will enable it by turning on the ASPEED_CLK_SDIO divisor. Signed-off-by: Joel Stanley [aj: Minor style cleanup] Signed-off-by: Andrew Jeffery --- drivers/clk/clk-aspeed.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 42b4df6ba249..898291501f45 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -500,9 +500,14 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; - /* SD/SDIO clock divider (TODO: There's a gate too) */ - hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, - scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + /* SD/SDIO clock divider and gate */ + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 15, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", + 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, soc_data->div_table, &aspeed_clk_lock); if (IS_ERR(hw))