From patchwork Mon Jun 10 17:10:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 166337 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1271961ilk; Mon, 10 Jun 2019 10:11:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqySUhgMITLTEi4TYP7FntYUFy8j0TmF8tYO9LoF0nNcRxcd0idNE+C5VxjiSiSEZI3urc0+ X-Received: by 2002:a17:902:ba88:: with SMTP id k8mr64134348pls.196.1560186695154; Mon, 10 Jun 2019 10:11:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560186695; cv=none; d=google.com; s=arc-20160816; b=goVqgU1y+mVbGh3+WLcNWCQJkmVx2eOj5Pf7tdil/WefaCfgZWpkoMdanlM0zuzmvb x0ipUJI58b+hrdPQl/Mm7ynR9FoRQ/zZivebgTFPzx1vTIjhnREu6u7xZI1O0odQV5qL HM1zA3/chHa8RJ+KIYkUAzCK2zYwHwlEQSOoQY141Hdx3RPVKTuPqL4FfrH9p2DJRfI0 bWgUkPIcSESz1RS5ThxTtfBJVoc2WhmoRNCBmmw84/of2Oc22MPv6jVM4tTFgE2MFbpN hNqkLFXU6bHXZvol1YfNdDgJy98rImFb25ZdL58mX4CVG4UdpOZfVb6aOCIzadSjSE98 u+7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=D2I3+AEazuZDhIiJtTZewtdd+cu8+rlLH2evSAkj3Tw=; b=r6Rpz0fTBblbEInlW+4otyuZbrSgVSWvgdpuwaTv8eY5/F3IaqdcpBTMEWHdFEtBvV nDx7/5OClZbfSd5Mls6VORTsZR4QfhmPjp7OKRx4qJRhWQP3NTJn9sA2k1XixncloJDM g8WCO2/8cKw3OsilKbkZFY0NjvkraBOoIUhIMhlu42sSV0Jw96JPxNHGaaS+GYox3hlR 1LNl5N3nmd+KWJIQkTpfikWfNMBWcT8bqzvigN533/OzCI0uYV1uv/7XfF8CJiGkTE1B BTDVB6GDs5OELLrhCA/1mQ+irLqh5gThdhOhKhw6Ambyww2dJwOIoXsVKFDi8HwbvpFr wjUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JWXZpp6N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o6si10539578plh.197.2019.06.10.10.11.34; Mon, 10 Jun 2019 10:11:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JWXZpp6N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387943AbfFJRLe (ORCPT + 30 others); Mon, 10 Jun 2019 13:11:34 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57586 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387415AbfFJRLc (ORCPT ); Mon, 10 Jun 2019 13:11:32 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x5AHBPLZ056820; Mon, 10 Jun 2019 12:11:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1560186685; bh=D2I3+AEazuZDhIiJtTZewtdd+cu8+rlLH2evSAkj3Tw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JWXZpp6NRv6TcJ8/UZOsqrxcN9z3o32GylrygV/NicsPJDfJHRZnz0MENPuek84// B9Zj8tHn+2822bu96Limhiyg9oDC36K1zynp/Zqk2hGwW+e5dlbfdkzrbuxwJ4bmtK h2ZQO7DWm3ncxNjgzvRDx1S1HDEdLPGuzGwnbnE8= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x5AHBPhw010006 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Jun 2019 12:11:25 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 10 Jun 2019 12:11:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 10 Jun 2019 12:11:25 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5AHBO7l050474; Mon, 10 Jun 2019 12:11:24 -0500 From: Grygorii Strashko To: Russell King , Linus Walleij , Tony Lindgren CC: Bartosz Golaszewski , , , , Santosh Shilimkar , Russell King , Grygorii Strashko Subject: [PATCH-next 02/20] gpio: gpio-omap: fix lack of irqstatus_raw0 for OMAP4 Date: Mon, 10 Jun 2019 20:10:45 +0300 Message-ID: <20190610171103.30903-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190610171103.30903-1-grygorii.strashko@ti.com> References: <20190610171103.30903-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Russell King Commit 384ebe1c2849 ("gpio/omap: Add DT support to GPIO driver") added the register definition tables to the gpio-omap driver. Subsequently to that commit, commit 4e962e8998cc ("gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()") added definitions for irqstatus_raw* registers to the legacy OMAP4 definitions, but missed the DT definitions. This causes an unintentional change of behaviour for the 1.101 errata workaround on OMAP4 platforms. Fix this oversight. Fixes: 4e962e8998cc ("gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()") Signed-off-by: Russell King Signed-off-by: Grygorii Strashko --- drivers/gpio/gpio-omap.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 2c6d46396834..44b214e5cefb 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -1457,6 +1457,8 @@ static struct omap_gpio_reg_offs omap4_gpio_regs = { .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, .irqstatus = OMAP4_GPIO_IRQSTATUS0, .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, + .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, + .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, .irqenable = OMAP4_GPIO_IRQSTATUSSET0, .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,