From patchwork Mon Jun 10 17:10:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 166336 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1271893ilk; Mon, 10 Jun 2019 10:11:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqx5GZRPv6EjhUquTEDL04U9U7FlSYICnBlcWKNeF8jGaqbAW5fR9SmN/LSMTthKNtqNbcoO X-Received: by 2002:a63:950d:: with SMTP id p13mr16535233pgd.269.1560186690966; Mon, 10 Jun 2019 10:11:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560186690; cv=none; d=google.com; s=arc-20160816; b=vsDk/kewd5J5Sxg/ZNeKrF39ecw0npBIrFT/CTvF9tk9B0Ey1XSeTOEtZiz4py4NUM zWwXZQS2wLNcsWi+VV1EszfWPYI0FoBV+PiC+Fh9HaAWUe49XCPd8noeKHcabvf1RVAx iONu2I4oB7k9tjgooL/ChLeu+E+JQPbfoJz341lOPuCMfZ3tWwfKxQcD4SAlDx+U5+s9 7YDDMMjs0iCOTdXCFw/I1ItXN7n9xr/7qERAMle0tpRUneSk9MyU5GEiVwydrDF4dXA4 LJC28b+8zGG8BGDpWtYUC+5fdQx9cWfFOlegcUhi8FoyUwx3gfi3jBJqMHBUwsSvukDW NWTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MosGYb3zQL/rr9NkvnZy2tg6gONUGVMX30Qu02oiURc=; b=Ku+RLQpCwQ6NFHcZG0bzHTt92RhFloO7seLATwEBn82Aw/sNKLlFXnoyUT3wLW2CMY Ri9ssh2DbPW3n/IjqxuL13xO+uyBxwOoBdJOf00GSuY1RjYz6Ef4UJtXkWOJRtGUUVXp CLLz8HvtOyPiDWbFawso2AsvSneiIph/NYyUHlamrLnb4XFC5dNeZWlb+lFqd3cPKTRU 2HU+rmqWev1/YDmQQUVsUpXRh20dJzJyC7+WN/82PEAeBmUaRs5OaFvks8Px5QkmpVeM 0pHjEbsi4FzFQH9cABEFwH2IJtBdm1dxeBnxW5KOGkienDYbvfC71guFnw9x9tDWy6SY 1ftQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="m1SZipH/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v9si9873284pgs.312.2019.06.10.10.11.30; Mon, 10 Jun 2019 10:11:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="m1SZipH/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387853AbfFJRL3 (ORCPT + 30 others); Mon, 10 Jun 2019 13:11:29 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44260 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387415AbfFJRLZ (ORCPT ); Mon, 10 Jun 2019 13:11:25 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x5AHBIuH121359; Mon, 10 Jun 2019 12:11:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1560186678; bh=MosGYb3zQL/rr9NkvnZy2tg6gONUGVMX30Qu02oiURc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m1SZipH/hzkCgk/uEsK6l98o3+22bdAH272uMzCjOmp/opcTnKIE1e5NDClTD0rxx ZXyj1tg91kiMF4ZHPWPCwVNE2Jalz8Y0C+57CinT7r916c0E42TLAOyfKwYgn86gc+ qBEYBPTxETTXiLNJvMHNsK+KT8p4GwDYTJh0UfTs= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x5AHBITi011699 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Jun 2019 12:11:18 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 10 Jun 2019 12:11:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 10 Jun 2019 12:11:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5AHBHRv066482; Mon, 10 Jun 2019 12:11:18 -0500 From: Grygorii Strashko To: Russell King , Linus Walleij , Tony Lindgren CC: Bartosz Golaszewski , , , , Santosh Shilimkar , Russell King , Grygorii Strashko Subject: [PATCH-next 01/20] gpio: gpio-omap: ensure irq is enabled before wakeup Date: Mon, 10 Jun 2019 20:10:44 +0300 Message-ID: <20190610171103.30903-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190610171103.30903-1-grygorii.strashko@ti.com> References: <20190610171103.30903-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Russell King Documentation states: NOTE: There must be a correlation between the wake-up enable and interrupt-enable registers. If a GPIO pin has a wake-up configured on it, it must also have the corresponding interrupt enabled (on one of the two interrupt lines). Ensure that this condition is always satisfied by enabling the detection events after enabling the interrupt, and disabling the detection before disabling the interrupt. This ensures interrupt/wakeup events can not happen until both the wakeup and interrupt enables correlate. If we do any clearing, clear between the interrupt enable/disable and trigger setting. Signed-off-by: Russell King Signed-off-by: Grygorii Strashko --- drivers/gpio/gpio-omap.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 16289bafa001..2c6d46396834 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -832,9 +832,9 @@ static void omap_gpio_irq_shutdown(struct irq_data *d) raw_spin_lock_irqsave(&bank->lock, flags); bank->irq_usage &= ~(BIT(offset)); - omap_set_gpio_irqenable(bank, offset, 0); - omap_clear_gpio_irqstatus(bank, offset); omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); + omap_clear_gpio_irqstatus(bank, offset); + omap_set_gpio_irqenable(bank, offset, 0); if (!LINE_USED(bank->mod_usage, offset)) omap_clear_gpio_debounce(bank, offset); omap_disable_gpio_module(bank, offset); @@ -870,8 +870,8 @@ static void omap_gpio_mask_irq(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&bank->lock, flags); - omap_set_gpio_irqenable(bank, offset, 0); omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); + omap_set_gpio_irqenable(bank, offset, 0); raw_spin_unlock_irqrestore(&bank->lock, flags); } @@ -883,9 +883,6 @@ static void omap_gpio_unmask_irq(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&bank->lock, flags); - if (trigger) - omap_set_gpio_triggering(bank, offset, trigger); - omap_set_gpio_irqenable(bank, offset, 1); /* @@ -893,9 +890,13 @@ static void omap_gpio_unmask_irq(struct irq_data *d) * is cleared, thus after the handler has run. OMAP4 needs this done * after enabing the interrupt to clear the wakeup status. */ - if (bank->level_mask & BIT(offset)) + if (bank->regs->leveldetect0 && bank->regs->wkup_en && + trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) omap_clear_gpio_irqstatus(bank, offset); + if (trigger) + omap_set_gpio_triggering(bank, offset, trigger); + raw_spin_unlock_irqrestore(&bank->lock, flags); }