From patchwork Fri May 31 14:33:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 165545 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp836802ili; Fri, 31 May 2019 07:33:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+N7NptkBWkljFseUevNbdh9ztsU/uBJpoJZMSWFbsAeCavrdDXTwv316z1r2m8b6gXz5C X-Received: by 2002:a17:902:b089:: with SMTP id p9mr10179658plr.38.1559313227908; Fri, 31 May 2019 07:33:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559313227; cv=none; d=google.com; s=arc-20160816; b=N3wq6+7gh62SExLC65kN8LpHE2h5rlBm41Q3IPkOk4D1tUZJ19jybjmMD7wIjSFB4D 42GRi0uqqCeO8aogqb8JuKtTqvnU+2S8hfCA0RBS3ktyizdHUX5QgSiMrBce0J/aC8cx 2MLtZNM8ylRri30OZsq0vCvyRVinCm7hdCsdhAIWhIAwUtXTwSqVCNwXzQYAAr/RyZZa W4rTJvaOE00B1USdLo4ZiBwshyQY+DI/frezet+8vfkfRSfDetsoMCFGTGhyJdovWawC nhevVlXaCOAHuumBhV/CGRAAJl4xM/uX2dUfROWGPELRQ3kKdxWV4CHMKV9sWePDJFz4 fnTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=9dUqXJPjhR62u0bbJ96kJMGG9uiX/WHXNWJr7JLytE0=; b=fTthbJF37F5HpqgvSZhv2VgFWTT/vgmtlAcpd1n6MzaBdRIQl6IScTHFq2phtc5XT6 EahQH1ocVwx+/7egly/iPrQKvI68hItIp/9hfj84FHezBlHXuWb6rSue3Ce4wHHoEa6P 3ZDY3TEGe5BlFzoYrGRQLDHeX3QkW5I9pPVHTaddW5Zmtv7/xuXpg0yA6M7yAhW+nbQH 2nB2IvSW6vpw35f5XS85KYKdFj2XeQ4gil6P6cU+cX8OXwmnIXWnGfiPLRc0vcZZTVNs NvnoK75ahNHyLMy5KqxPdv0hYlE1OMHYj5+pr+nOwDsh6jwf0Ghj+wHOCydoVQktiiRu tx7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m1si6508622pld.236.2019.05.31.07.33.45; Fri, 31 May 2019 07:33:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726849AbfEaOdo (ORCPT + 30 others); Fri, 31 May 2019 10:33:44 -0400 Received: from foss.arm.com ([217.140.101.70]:52470 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726823AbfEaOdm (ORCPT ); Fri, 31 May 2019 10:33:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FD911684; Fri, 31 May 2019 07:33:42 -0700 (PDT) Received: from usa.arm.com (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9FB433F5AF; Fri, 31 May 2019 07:33:40 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jassi Brar , Arnd Bergmann Cc: Sudeep Holla , Bjorn Andersson , Rob Herring , Mark Brown , Cristian Marussi , Jassi Brar , devicetree@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: mailbox: add bindings to support ARM MHU doorbells Date: Fri, 31 May 2019 15:33:17 +0100 Message-Id: <20190531143320.8895-4-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190531143320.8895-1-sudeep.holla@arm.com> References: <20190531143320.8895-1-sudeep.holla@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM MHU has mechanism to assert interrupt signals to facilitate inter-processor message based communication. It drives the signal using a 32-bit register, with all 32-bits logically ORed together. It also enables software to set, clear and check the status of each of the bits of this register independently. Each bit of the register can be associated with a type of event that can contribute to raising the interrupt thereby allowing it to be used as independent doorbells. Since the first version of this binding can't support doorbells, this patch extends the existing binding to support them by allowing "#mbox-cells" to be 2. Cc: Jassi Brar Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm-mhu.txt | 39 ++++++++++++++++++- 1 file changed, 37 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt index 4971f03f0b33..ba659bcc7109 100644 --- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt @@ -10,6 +10,15 @@ STAT register and the remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. +The MHU drives the interrupt signal using a 32-bit register, with all +32-bits logically ORed together. It provides a set of registers to +enable software to set, clear and check the status of each of the bits +of this register independently. The use of 32 bits per interrupt line +enables software to provide more information about the source of the +interrupt. For example, each bit of the register can be associated with +a type of event that can contribute to raising the interrupt. Each of +the 32-bits can be used as "doorbell" to alert the remote processor. + Mailbox Device Node: ==================== @@ -18,13 +27,21 @@ used by Linux running NS. - compatible: Shall be "arm,mhu" & "arm,primecell" - reg: Contains the mailbox register address range (base address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. +- #mbox-cells Shall be 1 - the index of the channel needed when + not used as set of doorbell bits. + Shall be 2 - the index of the channel needed, and + the index of the doorbell bit within the channel + when used in doorbell mode. - interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. + each of the 3 physical channels of MHU namely low + priority non-secure, high priority non-secure and + secure channels. Example: -------- +1. Controller which doesn't support doorbells + mhu: mailbox@2b1f0000 { #mbox-cells = <1>; compatible = "arm,mhu", "arm,primecell"; @@ -41,3 +58,21 @@ used by Linux running NS. reg = <0 0x2e000000 0x4000>; mboxes = <&mhu 1>; /* HP-NonSecure */ }; + +2. Controller which supports doorbells + + mhu: mailbox@2b1f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu", "arm,primecell"; + reg = <0 0x2b1f0000 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>; /* HP-NonSecure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client: scb@2e000000 { + compatible = "arm,scpi"; + reg = <0 0x2e000000 0x200>; + mboxes = <&mhu 1 4>; /* HP-NonSecure 5th doorbell bit */ + };