From patchwork Thu Apr 18 17:26:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 162513 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1013780jan; Thu, 18 Apr 2019 10:26:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwTFyfrIk/tuHp5cWR9AyfgG4j4um5FUFWhzi0xs73TtyvzBHp3AI351868dA+v0/oIhdTL X-Received: by 2002:a63:5a05:: with SMTP id o5mr2829889pgb.366.1555608402601; Thu, 18 Apr 2019 10:26:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555608402; cv=none; d=google.com; s=arc-20160816; b=jYoB7m7FUkfACJn1lHaGrrLNyauoF5hIPzCxUr0djuYS4F08u1534J6qzUntcbDplZ Hg4e6YViwOxZ7U251dUHB6hx8qDDDpc+KMXTnc0Sx/peBHPjonQodVnDzfVIK1dyIe1A e0fOnZgLVGO7dZIVhFWXGmTaR96dq7S6oh5PNvFrfoNHBJhn8fL3wKAhwMFsZTMpMtZv VX6Bd8S4N1JFzcmgeyFVqj8nypXAkGeys2X0y6wcY3hzrwz9os0U1ldAR0uNJ+Ecyhgf 3cvM55TlIF3rM64517teX9fmaNoU8y/n2G8FIw5UbLKbh4VDB7SSnzlFioWyHESmCdN0 kBuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=gbOuErGQg7KTYOu1kjoc5w9S3YvTNk1VWi7/xX2Dq28=; b=osAMCUjLUdJ8SUUf1j64iu/VPzapHwTd7UsrWuNYznS3WPVAo3frG9Myp1fsVSVpfw 1d//grv3ZUkvvmn5p1Ew3/32fOYtfXk9L2HlDpjzGtUKvdvdUx6J0nTk8mTBcbUEiWMQ rQ7E1TovU2I1HZJSis4wq/IE5INxzPTeEqXVUy4/1l2Ufk11kNRp29EBhJ9bbIp0wNLS 7/GZysbFnKW39SDWPu+oHmPi7Yis3qWC0Yo7sh3/jR5/OqD5PpMbVbS8k3int631YVGG Q8asUS1DC3kik4sayzbe+QceSOuPvzKK9WT2VxVQdk5P8oCOpciran29LDBiVL1Y4SpW 4rng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bj1si2596071plb.214.2019.04.18.10.26.42; Thu, 18 Apr 2019 10:26:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389898AbfDRR0k (ORCPT + 30 others); Thu, 18 Apr 2019 13:26:40 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:38138 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389881AbfDRR0g (ORCPT ); Thu, 18 Apr 2019 13:26:36 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0BCBA169E; Thu, 18 Apr 2019 10:26:36 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6FCD3F557; Thu, 18 Apr 2019 10:26:33 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org Cc: logang@deltatee.com, douliyangs@gmail.com, miquel.raynal@bootlin.com, marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de, joro@8bytes.org, robin.murphy@arm.com, bigeasy@linutronix.de, linux-rt-users@vger.kernel.org, Julien Grall Subject: [PATCH 6/7] irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg Date: Thu, 18 Apr 2019 18:26:10 +0100 Message-Id: <20190418172611.21561-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190418172611.21561-1-julien.grall@arm.com> References: <20190418172611.21561-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The functions mbi_compose_m{b, s}i_msg may be called from non-preemptible context. However, on RT, iommu_dma_map_msi_msg requires to be called from a preemptible context. A recent patch split the function iommu_dma_map_msi_msg in 2 functions: one that should be called in preemptible context, the other does not have any requirement. This patch reworks the GICv3 MBI driver to avoid executing preemptible code in non-preemptible context by preparing the MSI mappings when allocating the MSI interrupt. Signed-off-by: Julien Grall --- drivers/irqchip/irq-gic-v3-mbi.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index fbfa7ff6deb1..c812b80e3ce9 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -84,6 +84,7 @@ static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq, static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { + msi_alloc_info_t *info = args; struct mbi_range *mbi = NULL; int hwirq, offset, i, err = 0; @@ -104,6 +105,16 @@ static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, hwirq = mbi->spi_start + offset; + err = iommu_dma_prepare_msi(info->desc, + mbi_phys_base + GICD_CLRSPI_NSR); + if (err) + return err; + + err = iommu_dma_prepare_msi(info->desc, + mbi_phys_base + GICD_SETSPI_NSR); + if (err) + return err; + for (i = 0; i < nr_irqs; i++) { err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i); if (err) @@ -142,7 +153,7 @@ static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); msg[0].data = data->parent_data->hwirq; - iommu_dma_map_msi_msg(data->irq, msg); + iommu_dma_compose_msi_msg(data->irq, msg); } #ifdef CONFIG_PCI_MSI @@ -202,7 +213,7 @@ static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg) msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); msg[1].data = data->parent_data->hwirq; - iommu_dma_map_msi_msg(data->irq, &msg[1]); + iommu_dma_compose_msi_msg(data->irq, &msg[1]); } /* Platform-MSI specific irqchip */