From patchwork Mon Apr 15 21:21:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 162277 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3418491jan; Mon, 15 Apr 2019 14:22:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxvLpw9hcU6AWaf1s+lEZrqWwrStG5xGaSN+Y0+dKiEuf2IwWpZY+jKk8ja5hklRKXGAJl3 X-Received: by 2002:a63:f115:: with SMTP id f21mr67331437pgi.65.1555363328789; Mon, 15 Apr 2019 14:22:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555363328; cv=none; d=google.com; s=arc-20160816; b=L1OwZxegageKP8VCS3oFcj05hmbRrti9xT72okWOucBm208l50zlKmr6uxtq4JkUQx 2BdCRAV280ezm3WbYZKsbpW4tkxETXm2J9Wj/2HbRAy0eq2m38l3C7dAy+GGVoSjiP4W 3MjemZgjfcWaHmk/ovDkv/SgTSiYG+yVTNmUFT3FHh2n3XJPqA4SOy6w5hMiW/lPucTN sISssPDKoisrNlk5PaK3OvR7PSrHaHpVGZrwe3mbd3qDZ2kN5H748Zl6ORuHjS8r5B/o qnCifb0JpnNUgax8UQLqWqhrs/sMumdd9AP+Ppe71t1M/hkx/L2hIhN/DbLdRE73xq8H UGfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ccTWvIJePO3wJVksu7m93zMwGxHKarWYm3YSINZmFF0=; b=ddonsBAMcjrb+G4P41xJ+S2vFwOjkCz/T3s3UWhkqRsk+KnoP14zkuvlzMqpPwXmEO MTOLzbXzg8yQBc0kZFZ/KTQzlReedkX8YB4HWt9h7tqmoxKWMc59CeqdfCSuuUZVcngq Arqn4x2mxyjc79b4MDDkdnH6PcTLe8pK5rO12P9Esc+j++rygRdRSwFqpreo+zvW3vpU kxVimCX9CFug/wdC0OurKjPw+RV10LvIZOJ3TrW7Urw7kSDgueM751QATDkBe++4NBjv Xr2/6rAKjiwX4gUPGOr/1Vgkk9XNsQdFvQmLV7NwSMzdySsDivnRTdz1VwxN0F2FYG2E LA6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s3si26670895plb.93.2019.04.15.14.22.08; Mon, 15 Apr 2019 14:22:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728142AbfDOVWC (ORCPT + 30 others); Mon, 15 Apr 2019 17:22:02 -0400 Received: from foss.arm.com ([217.140.101.70]:42962 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728045AbfDOVVo (ORCPT ); Mon, 15 Apr 2019 17:21:44 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 401CC1684; Mon, 15 Apr 2019 14:21:44 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 989AE3F68F; Mon, 15 Apr 2019 14:21:43 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2se.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Andre Przywara Subject: [v8 08/10] arm64: Always enable ssb vulnerability detection Date: Mon, 15 Apr 2019 16:21:27 -0500 Message-Id: <20190415212129.1112-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190415212129.1112-1-jeremy.linton@arm.com> References: <20190415212129.1112-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ssb detection logic is necessary regardless of whether the vulnerability mitigation code is built into the kernel. Break it out so that the CONFIG option only controls the mitigation logic and not the vulnerability detection. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Reviewed-by: Catalin Marinas Tested-by: Stefan Wahren --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 11 +++++++---- 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index e505e1fbd2b9..6ccdc97e5d6a 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -638,11 +638,7 @@ static inline int arm64_get_ssbd_state(void) #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e51ddcb197c0..5814645afd73 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -275,7 +275,6 @@ static int detect_harden_bp_fw(void) return 1; } -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -346,6 +345,7 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, *updptr = cpu_to_le32(aarch64_insn_gen_nop()); } +#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state) { if (this_cpu_has_cap(ARM64_SSBS)) { @@ -370,6 +370,12 @@ void arm64_set_ssbd_mitigation(bool state) break; } } +#else +void arm64_set_ssbd_mitigation(bool state) +{ + pr_info_once("SSBD disabled by kernel configuration\n"); +} +#endif /* CONFIG_ARM64_SSBD */ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, int scope) @@ -467,7 +473,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } -#endif /* CONFIG_ARM64_SSBD */ static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) @@ -759,14 +764,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, }, -#endif #ifdef CONFIG_ARM64_ERRATUM_1188873 { /* Cortex-A76 r0p0 to r2p0 */