From patchwork Wed Apr 10 23:12:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 162051 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp6763452jan; Wed, 10 Apr 2019 16:13:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJf+F0XvPZtzwuDbJ7w4CbkUWZU8nXa3h7tZ5JOM1x7Li9ZLoQCudCjZZuOTbH0aKMZ0nF X-Received: by 2002:a63:6942:: with SMTP id e63mr44206733pgc.102.1554938014165; Wed, 10 Apr 2019 16:13:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554938014; cv=none; d=google.com; s=arc-20160816; b=08s9zfY/LGwTnoFdWzMFZKxs6Qq4Zb+hokKt+T4A1CGwpl/Rb5pFU4FFDpaY6A++CG 5yrfjGcFPInRKfAk0SZTWdsAhJjf2V9mybnhNdC1NBURXUFs+fo3bTBP0IyQrhMmxTBy pAREmNYlr6yYW3HFxp+GO1QR1VZmn8s1DGOMMz7e97rbqcBLY2SY1QlXbynmIhZbuf8n JUxuFj1oHceRWY0MwdXHWcwC1Lbu5d15R/pTHP2GQAJb/7x2zpXIbmGOH469cDndPEYS 9HQF52pUA31iK/VR6C8SK4LCSgL7nbDAdmWnXVfmDZyPF9Fpq8sMT69arDleCIScml9U LCfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=QxQC4phGQCHQ5Vpy/JyRv9S0ZLIy7+bnkoVTorPOaQA=; b=VutVwoM1sCOQIvEHDSMPbC9srZrTz+wgEW3Yt2KIbAQUw+BRjin1JniS+/ZjCoDbiC 5mNDWA/S7Chf4VcNQqyei3EeRSsY+bsPMGfL1DXPmCT6f3NB4w9QRjky8uCLo3mbu3bN 77D8S/vDxbrK4wue4Ysi5ZeMMfEdXCgRwlkrydCJlG2NsK92F/kfaCUcvXZ3DlsK23tH AVPmB3gyxF4XnAcwVkXgdz0fc2WQTS7cQ7d7OVhoOtL9N9wAuaO8FJbwXNxGnmCYfwQX OWUOpMO6MP/Ui0QR5X/Bz2o1TOD7B8yWRQw9nnUv4hvsVfy8+biLwJjsxwOqi5WtU/oF kkFQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a22si33446529pfc.217.2019.04.10.16.13.33; Wed, 10 Apr 2019 16:13:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726951AbfDJXNX (ORCPT + 31 others); Wed, 10 Apr 2019 19:13:23 -0400 Received: from foss.arm.com ([217.140.101.70]:33038 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726827AbfDJXM6 (ORCPT ); Wed, 10 Apr 2019 19:12:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37BE616A3; Wed, 10 Apr 2019 16:12:58 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8E1C43F557; Wed, 10 Apr 2019 16:12:57 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2se.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Andre Przywara Subject: [v7 06/10] arm64: Always enable spectrev2 vulnerability detection Date: Wed, 10 Apr 2019 18:12:33 -0500 Message-Id: <20190410231237.52506-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410231237.52506-1-jeremy.linton@arm.com> References: <20190410231237.52506-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sysfs patches need to display machine vulnerability status regardless of kernel config. Prepare for that by breaking out the vulnerability/mitigation detection code from the logic which implements the mitigation. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Reviewed-by: Catalin Marinas Tested-by: Stefan Wahren --- arch/arm64/kernel/cpu_errata.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e5c4c5d84a4e..74c4a66500c4 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -109,7 +109,6 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused) atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1); -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR #include #include @@ -270,11 +269,11 @@ static int detect_harden_bp_fw(void) ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) cb = qcom_link_stack_sanitization; - install_bp_hardening_cb(cb, smccc_start, smccc_end); + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) + install_bp_hardening_cb(cb, smccc_start, smccc_end); return 1; } -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); @@ -513,7 +512,6 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE_LIST(midr_list) -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR /* * List of CPUs that do not need any Spectre-v2 mitigation at all. */ @@ -545,6 +543,11 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) if (!need_wa) return false; + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { + pr_warn_once("spectrev2 mitigation disabled by configuration\n"); + return false; + } + /* forced off */ if (__nospectre_v2) { pr_info_once("spectrev2 mitigation disabled by command line option\n"); @@ -556,7 +559,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) return (need_wa > 0); } -#endif #ifdef CONFIG_HARDEN_EL2_VECTORS @@ -731,13 +733,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), }, #endif -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = check_branch_predictor, }, -#endif #ifdef CONFIG_HARDEN_EL2_VECTORS { .desc = "EL2 vector hardening",