From patchwork Wed Apr 10 23:12:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 162047 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp6763197jan; Wed, 10 Apr 2019 16:13:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqzbU3iGBNe4C0P83sUK9/zLbesbqw7Ao7m0pgUeUFvD2p+sy1++rYc8VPTaF5bD156I22cJ X-Received: by 2002:a62:6807:: with SMTP id d7mr45214619pfc.75.1554937991192; Wed, 10 Apr 2019 16:13:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554937991; cv=none; d=google.com; s=arc-20160816; b=q119EnXu2GrvfkhcG7qnzWXePLMg0gj3RsE+Eq4XSp6yRT8TxZg7u95/dghOeA2W16 bRntRhMTgzDiLcpuKV8j3YV7JFFKqb6ItGGbDjQ2zj1apBmaGSJfymUo7GdrV7U/xhXT WzQ7urqC+ZTTJ5+CW6nu5TOTMlS7Q0RCFH6atMkn10ipU8FNrP6336kGh51RRKXwiwSG xH+xxK62YEKEwu1rpwu75OBC9+LSay28LWa6jozTdX+rMQM41FImxSAy4oTWGQvVczu5 ZYYDcgqcqVvcSTsGdz32iGdgTdvUNvJnLcf1Whcq9HilPjWK+No2FQSU99ZQUdpjkwC7 LdCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=JfHrshB1h8F+SNt65S4RsvArHFtI95AHxu/tN13BdW4=; b=yMaFJahh//5/nuPQsIrp0orsPzdewfjbavgrThJ00qdV0luTf6KUp7FBJuqRKJRGDn 1uaCHXPIaI/MKNX0hYFqhh1GFiefv6IovrGpZwRA4uw32VgnHaBREYvUrArdEC/agmiO ep0Le7E9AcI2AM5ERWE1nw94SdkrSZ4Bdxk49L3AlpXR6mXL218sWV9SjubFQtPGAko3 Qd13syez9fPuGZu8Gl/+VAbLJHu6NBRuwYWlRZ19OTc0/a4Qwl+3wkbXe71aGGz/U9Nq JpW9LZqZXHvB+jbFAvuGxa/uqmADai9+oBUyWe/5+wmr6OCTvpH9v89myqL5CfMqSXZ8 k4dQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3si34249665plx.386.2019.04.10.16.13.10; Wed, 10 Apr 2019 16:13:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726912AbfDJXNJ (ORCPT + 31 others); Wed, 10 Apr 2019 19:13:09 -0400 Received: from foss.arm.com ([217.140.101.70]:33064 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726843AbfDJXNA (ORCPT ); Wed, 10 Apr 2019 19:13:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 30937374; Wed, 10 Apr 2019 16:13:00 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8FEDF3F557; Wed, 10 Apr 2019 16:12:59 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2se.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [v7 09/10] arm64: add sysfs vulnerability show for speculative store bypass Date: Wed, 10 Apr 2019 18:12:36 -0500 Message-Id: <20190410231237.52506-10-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410231237.52506-1-jeremy.linton@arm.com> References: <20190410231237.52506-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return status based on ssbd_state and the arm64 SSBS feature. If the mitigation is disabled, or the firmware isn't responding then return the expected machine state based on a whitelist of known good cores. Given a heterogeneous machine, the overall machine vulnerability must be a tristate to assure any vulnerable cores transition to vulnerable and stay there. Further, we delay transitioning to vulnerable until we know the firmware isn't responding to avoid a case where we miss the whitelist, but the firmware goes ahead and reports the core is not vulnerable. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 62 ++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) -- 2.20.1 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6958dcdabf7d..a1f3188c7be0 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -278,6 +278,13 @@ static int detect_harden_bp_fw(void) DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; +static enum {SSB_UNSET, SSB_SAFE, SSB_UNSAFE} __ssb_safe = SSB_UNSET; + +static inline void ssb_safe(void) +{ + if (__ssb_safe == SSB_UNSET) + __ssb_safe = SSB_SAFE; +} static const struct ssbd_options { const char *str; @@ -383,16 +390,25 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, struct arm_smccc_res res; bool required = true; s32 val; + bool this_cpu_safe = false; WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); if (this_cpu_has_cap(ARM64_SSBS)) { required = false; + ssb_safe(); goto out_printmsg; } + if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list)) { + ssb_safe(); + this_cpu_safe = true; + } + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) { ssbd_state = ARM64_SSBD_UNKNOWN; + if (!this_cpu_safe) + __ssb_safe = SSB_UNSAFE; return false; } @@ -409,6 +425,8 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, default: ssbd_state = ARM64_SSBD_UNKNOWN; + if (!this_cpu_safe) + __ssb_safe = SSB_UNSAFE; return false; } @@ -417,23 +435,31 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, switch (val) { case SMCCC_RET_NOT_SUPPORTED: ssbd_state = ARM64_SSBD_UNKNOWN; + if (!this_cpu_safe) + __ssb_safe = SSB_UNSAFE; return false; + /* machines with mixed mitigation requirements must not return this */ case SMCCC_RET_NOT_REQUIRED: pr_info_once("%s mitigation not required\n", entry->desc); ssbd_state = ARM64_SSBD_MITIGATED; + ssb_safe(); return false; case SMCCC_RET_SUCCESS: + __ssb_safe = SSB_UNSAFE; required = true; break; case 1: /* Mitigation not required on this CPU */ required = false; + ssb_safe(); break; default: WARN_ON(1); + if (!this_cpu_safe) + __ssb_safe = SSB_UNSAFE; return false; } @@ -474,6 +500,14 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } +/* known invulnerable cores */ +static const struct midr_range arm64_ssb_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + {}, +}; + static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) { @@ -769,6 +803,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, + .midr_range_list = arm64_ssb_cpus, }, #ifdef CONFIG_ARM64_ERRATUM_1188873 { @@ -807,3 +842,30 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, return sprintf(buf, "Vulnerable\n"); } + +ssize_t cpu_show_spec_store_bypass(struct device *dev, + struct device_attribute *attr, char *buf) +{ + /* + * Two assumptions: First, ssbd_state reflects the worse case + * for heterogeneous machines, and that if SSBS is supported its + * supported by all cores. + */ + switch (ssbd_state) { + case ARM64_SSBD_MITIGATED: + return sprintf(buf, "Not affected\n"); + + case ARM64_SSBD_KERNEL: + case ARM64_SSBD_FORCE_ENABLE: + if (cpus_have_cap(ARM64_SSBS)) + return sprintf(buf, "Not affected\n"); + if (IS_ENABLED(CONFIG_ARM64_SSBD)) + return sprintf(buf, + "Mitigation: Speculative Store Bypass disabled\n"); + } + + if (__ssb_safe == SSB_SAFE) + return sprintf(buf, "Not affected\n"); + + return sprintf(buf, "Vulnerable\n"); +}