From patchwork Tue Mar 26 22:39:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 161235 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5766169jan; Tue, 26 Mar 2019 15:40:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqzriplHNs8s+lwDDmsKvOmW4AdS/rM6cF4sk70W1sqOGR7hBJ1aQaz5tPNgO+BKaBFarByX X-Received: by 2002:a17:902:b58f:: with SMTP id a15mr19537028pls.36.1553640007478; Tue, 26 Mar 2019 15:40:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553640007; cv=none; d=google.com; s=arc-20160816; b=gBiJBM+/rKo/vGVCHG91FYNA9wr3N8QoO9PpegPP8Am9kjiTJFrtJLgp5+deqfupBH VqCfs+zS7/LhTggoXwoqYkgDzQFn7tNLtLaZiYMG/NXCceMD1BSWyxOoeo6SimMUFWfL ou96fwb0jeq8pDSwGVuXJz9xTB3q0jIJcTbNvkV+d8Jp2Iibnw1FXAGiaVS+KJSRItCG ohUqboZsam1QN0bIm87aWxIaiiJfUBGH2EN9mXVVxnFcZfQC5Fs7HEFBAMCWY60NmHVK eGw7Tl1qlvEVkF86cmXTFTSPRQGNTHk+UsQybF1K6LuPSkQQnEp24Oys4uOZCKuF2Mv+ +FGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lZQhCPtni8aaOP+OEH9YfW3qq14wlIvFUy66wuPXgJw=; b=Yb8y4PCaQLtut46e8pRsL4P8UJrPOWjYgbX2NU3X80iYoRIXCg4YdnGB+og7uTtBw7 Z3mj3gIZmiK7g1hJwX3LgRmPdF7zS1Uj0JfM/pJbL8WnN5btivGB3KdwaN9uvefyHdxm 1Zi4QheD4KIsPRysNvz0rbikflkTwYpmnyp8NE8fJRukXP5OoxD2TcBqQlJpLhMpdxrL i1Nfqo1F+tSuGUtKgJIX5G84KOeQDnO1jOVcEP2+C+V4SRh6Lz9xM9mZks4CjGs0lG76 uOc4R4gd8VvCpGwjMy/NEpKEiIvk3eH0lEx7t8LCFa88MIoCUhrwDnKZW0Dv+Wi45r9U +jTg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b9si16243084pfd.228.2019.03.26.15.40.07; Tue, 26 Mar 2019 15:40:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732157AbfCZWj7 (ORCPT + 31 others); Tue, 26 Mar 2019 18:39:59 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44508 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726782AbfCZWj5 (ORCPT ); Tue, 26 Mar 2019 18:39:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F158A1682; Tue, 26 Mar 2019 15:39:56 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5ED093F614; Tue, 26 Mar 2019 15:39:56 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, lenb@kernel.org, mark.rutland@arm.com, sudeep.holla@arm.com, james.morse@arm.com, lorenzo.pieralisi@arm.com, linuxarm@huawei.com, Jeremy Linton Subject: [PATCH 3/4] arm_pmu: acpi: spe: Add initial MADT/SPE probing Date: Tue, 26 Mar 2019 17:39:37 -0500 Message-Id: <20190326223938.5365-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190326223938.5365-1-jeremy.linton@arm.com> References: <20190326223938.5365-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI 6.3 adds additional fields to the MADT GICC structure to describe SPE PPI's. We pick these out of the cached reference to the madt_gicc structure similarly to the core PMU code. We then create a platform device referring to the IRQ and let the user/module loader decide whether to load the SPE driver. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/acpi.h | 3 ++ drivers/perf/arm_pmu_acpi.c | 69 +++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) -- 2.20.1 diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 7628efbe6c12..d10399b9f998 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -41,6 +41,9 @@ (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \ (unsigned long)(entry) + (entry)->header.length > (end)) +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \ + spe_interrupt) + sizeof(u16)) + /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI pgprot_t __acpi_get_mem_attribute(phys_addr_t addr); diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c index 0f197516d708..a2418108eab2 100644 --- a/drivers/perf/arm_pmu_acpi.c +++ b/drivers/perf/arm_pmu_acpi.c @@ -74,6 +74,73 @@ static void arm_pmu_acpi_unregister_irq(int cpu) acpi_unregister_gsi(gsi); } +static struct resource spe_resources[] = { + { + /* irq */ + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device spe_dev = { + .name = "arm,spe-v1", + .id = -1, + .resource = spe_resources, + .num_resources = ARRAY_SIZE(spe_resources) +}; + +/* + * For lack of a better place, hook the normal PMU MADT walk + * and create a SPE device if we detect a recent MADT with + * a homogeneous PPI mapping. + */ +static int arm_spe_acpi_parse_irqs(void) +{ + int cpu, ret, irq; + int hetid; + u16 gsi = 0; + bool first = true; + + struct acpi_madt_generic_interrupt *gicc; + + /* + * sanity check all the GICC tables for the same interrupt number + * for now we only support homogeneous ACPI/SPE machines. + */ + for_each_possible_cpu(cpu) { + gicc = acpi_cpu_get_madt_gicc(cpu); + + if (gicc->header.length < ACPI_MADT_GICC_SPE) + return -ENODEV; + if (first) { + gsi = gicc->spe_interrupt; + if (!gsi) + return -ENODEV; + hetid = find_acpi_cpu_topology_hetero_id(cpu); + first = false; + } else if ((gsi != gicc->spe_interrupt) || + (hetid != find_acpi_cpu_topology_hetero_id(cpu))) { + pr_warn("ACPI: SPE must be homogeneous\n"); + return -EINVAL; + } + } + + irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, + ACPI_ACTIVE_HIGH); + if (irq < 0) { + pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi); + return irq; + } + + spe_resources[0].start = irq; + ret = platform_device_register(&spe_dev); + if (ret < 0) { + pr_warn("ACPI: SPE: Unable to register device\n"); + acpi_unregister_gsi(gsi); + } + + return ret; +} + static int arm_pmu_acpi_parse_irqs(void) { int irq, cpu, irq_cpu, err; @@ -279,6 +346,8 @@ static int arm_pmu_acpi_init(void) if (acpi_disabled) return 0; + arm_spe_acpi_parse_irqs(); /* failures are expected */ + ret = arm_pmu_acpi_parse_irqs(); if (ret) return ret;