From patchwork Mon Mar 25 09:39:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161072 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751164jan; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxqCJmI3jMPzEc+q0v7xTkIMFRuAqz4/MqQKTvJ6lA52Vyg8ZIDH9Tdz+s1ur1VKFI4mULM X-Received: by 2002:a17:902:7e05:: with SMTP id b5mr11568906plm.127.1553507061485; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507061; cv=none; d=google.com; s=arc-20160816; b=V5vCV6S9tEZDG2Fr2AXmJ1c0SasX8jrsnCfEmJC4oEx3+J7EXnplXudEG+rnY0rWzU jF2OVOX2qN6lUFTHrZNhr5BItSe2uxnqCuVrNkv7KcVbGqGVB4LnMBbvIXJdFS0YbdUM iVx1H1GY81a2Vk+GArGyEC5iyD7x8TazZL19xvJPrHPSHmZgWN8kRUQpoUJ52f6voJ6N AswC26Wbz2+spmuhIWviO2PKSzGa+Qc7uCE+6BUG4wrQmXYfpKLaDoNeC/kRDgPbP1KM qI8Y8vD/oLr8kTGF8K1Tz6rbxodJvKQRklzkho5Op+iM1kAHShknzUiKQc2yDpCJUArN DRnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; b=Fcl4NbCdUr0S0J9uUVJMT2OV1KZwhXLrDmJpaOOsJIYGcvFQ72ioDyQgAA/YI/VKmC JDeJUm2ZLfp2zGL/8kleosZGpIZ1td9nXXvLmia1r36EDYhlntVr6lTEihb2rhcrHQyT Jf2ntJnj4PunmlkZj4ntk927ac1m6ubO9Dbi1b1OuU+pNrR05MxzzZK5xeAACzMXVgG9 kvdwoVTLgDeowonVdLQ/9DEMvAD5YkUcU9y5vmNGKwjlTfuwE7eQzc1QJatEEgNj52J2 sIO2S52yWMT/copTBVJ0EnNtDm+SoBh5moEOLHn5kBZIbWZ4w0qIuWJUxEh62AIhIryu 3tqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Xx+6TG67; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j13si7186424pgm.73.2019.03.25.02.44.21; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Xx+6TG67; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730818AbfCYJoU (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:20 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45176 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730757AbfCYJoR (ORCPT ); Mon, 25 Mar 2019 05:44:17 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hvfM068411; Mon, 25 Mar 2019 04:43:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507037; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Xx+6TG67rlTZNWox5cCKm1CIXzIrJ/3ZGkd8A/+4NfqEMvyrzKYWZXv2evRtDV8Pa EODDlHSveYHeGXIsPucosbjNEP+p8itvmSkLMZvoDzzs6Yp/ut/y/i7FA2btMFsrem MxD0Uk3prVEHLuOnwIFyXgyNxnB4RQKhCSRUBkxw= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hvR5055269 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:57 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:56 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9fead028077; Mon, 25 Mar 2019 04:43:52 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 24/26] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 25 Mar 2019 15:09:45 +0530 Message-ID: <20190325093947.32633-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0c208b9bda43..2bf5a35c0570 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);