From patchwork Mon Mar 25 09:39:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161076 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751599jan; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwYSDtYKwv0rDZTf3ypjfzR0P0d/xPaMEDYhQrsEAFyv/3Vx37q84bMQx+hKwjSpApE3iMk X-Received: by 2002:a17:902:8c8b:: with SMTP id t11mr23842907plo.148.1553507094609; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507094; cv=none; d=google.com; s=arc-20160816; b=vqQqIqoShPhTh/WkvZ5inTgqGjHHULF9Oy61G/h8JKg0GklOIIGbCaRpCOl3fBqupA tWKvOqkfLse6m4IQmOHVBFaiFmJqyusxpuDyI5V1q/PaEeJkbvh7kGeQ8FWzzZEgjbfu Azh6lzXElZkBR8meZBZz+fjuLN/y0pe1CLKSXw5NOpI4CR9ICFxUpo6Nsu09QoPYv5+/ wFdL1gRPxgtAk48MijBL+CG5Dw3bFUKtUbwJmHI7SuIKhvs941HLf0qbvvker29TaI2X MvulNEUREJtM1NbzKc+N3Xt4cSe84pwsaLnOO0Y9+Sjprhr0zgZkkdPZVW1Ohhb98sBV kNeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; b=M4Gh6ZBFD4a4CjFIXUmNMZd4U3vFfgSITWGNfFZ7mb6QGykmNSfFR0Z4rt/GHOANTK hni44WPZizaSsq9bYxcL9V9qEBLpykrQqFUlODCkfQyyfqbnl5N+bLD0ZCYMlKRhiE/6 QoPYoh2nyWvaIyZH8B9gWb/lbgPgcRPdhSJ1z4PBT6s8yEMD11TK3rBZU/Q6CW/09g0o YbeB/SfujvyQQWTd4TxtRLNzId5P6u9/oW+nx9ax9JAH0skvIefwdwrEHHGWdvwFb4DV eEWh5CF2dTEkP7j3s8THYVSDi6J1DHkB1vBNRegMmauVBpNl3N6lXk87FcgCUluWfQYm kPjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dib0lyw+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6si13226846pfc.201.2019.03.25.02.44.54; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dib0lyw+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730861AbfCYJox (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:53 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46586 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730540AbfCYJou (ORCPT ); Mon, 25 Mar 2019 05:44:50 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hqXh075705; Mon, 25 Mar 2019 04:43:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507032; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dib0lyw+ZZqLtvVBmb5/4k//xg5E4076Nq4KJt1KEAdB5hG/zd3Vd1EpTGklXVhn+ OB5+s1HlAyusd4nU+xCy35xbFCdBBM8dZXOpeFDzy35IcCTz6aNj4qHLg1Ucwu8Ksl KFoXHMXag9F+pDbpDsC+1/cQMB54x4AUFIPFiKgk= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hqAV111677 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:52 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:51 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feac028077; Mon, 25 Mar 2019 04:43:46 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size Date: Mon, 25 Mar 2019 15:09:44 +0530 Message-ID: <20190325093947.32633-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Configure RESBAR capability to advertise the smallest size (1MB) for couple of reasons. A) Host side resource allocation of BAR fails for larger sizes. B) Endpoint function driver does not allocate memory for all supported sizes in RESBAR capability. If and when there is a usecase required to add more flexibility using RESBAR, this can be revisited. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 74477ad7467f..0c208b9bda43 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + int dw_pcie_ep_init(struct dw_pcie_ep *ep) { + int i; int ret; + u32 reg; void *addr; + unsigned int nbars; + unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; @@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); return 0;