From patchwork Mon Mar 25 09:39:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161070 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751001jan; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqysxsqlN1BpKOyj9rUtjISWVCGtcFypyBZJykZbFtP6wPM+QTALLbK6cqpY5JKsgZQYMTnK X-Received: by 2002:a17:902:758f:: with SMTP id j15mr24255886pll.211.1553507046589; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507046; cv=none; d=google.com; s=arc-20160816; b=dZDTwk2ntTq7akOEkwibiEk+KgUiHj9DaSWrLfri224eoC2+8B3iof3v754ZrNLG+i 83u/9T1JA5UWY3HHT5GLLA9KbM0Esb4DbVGVH1wjTA2BK190uLzJbDTSzWZSHf2rSOKk 9gT/PGMHlDxmeAl+YklGW6p2GCe8P97H2I7umgeKmFeC0TTSg9NTNUO61QAbT2VACInH gVODzPlwbN+oqbGIx0kq3qdk4sW017Xe+41jOccqA8fmfXT1WroDDnlmOH6xLMaxr6oJ b2E1pKWo0mGAvZYyHhc+1tlqWyoMnYhb7Ta/eIjpygnYU1oiCgreIoPfi6bz2Bs6Clrc cA4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; b=OGTqFwlvrBJQKs0qz4UoWxuTp2w8XO62pATwLJuUzLLnaI9jnzo/Gi6XCPRZ9iKOud URnhw/tGJuMchLM43ehFp927csLzoDzWIoAUHOVGtI2eahkp1+klL6QZrZs6ckZ6KoIB NH1D2VeqDBaTmSHafnyn8bopN9uWOiKR6D+NU7urqYY/Lm1FfoaLlWUIGwL0G61o8DvW 9WztfwdkrIVYBKYJFrtPXsVuoUzFjUt0daVrayEqKpHsRBXKwbegVjnKsljT8HlrDdAk DU9gYjVaOciKoqjptnzxT2JfnHL1gpu0xl6PwH4v5Q+vpH7829HWLf/lwOcMZoeW/1PA XQAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lk0jUiMT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e67si14744205plb.107.2019.03.25.02.44.06; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lk0jUiMT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730766AbfCYJoF (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33588 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730332AbfCYJoD (ORCPT ); Mon, 25 Mar 2019 05:44:03 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hZ77011109; Mon, 25 Mar 2019 04:43:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507016; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lk0jUiMTO3bL980SrgGsvlkPHcorS0hl3VaUCKbJoAfkqj6xXOv+du67c1KxSu2dV /S4+iDcjCrq1XoaWiAtkq+h/swtVcOfHVJ8wGj5BwllEPUDJgU9tf8W4z+l6xKO6J5 sZe2RPj+Sxe/EXMW5My1ycpdTsk3F5XBe3d+7DtQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hZRt054894 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:35 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaZ028077; Mon, 25 Mar 2019 04:43:30 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 25 Mar 2019 15:09:41 +0530 Message-ID: <20190325093947.32633-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dc6a4bbd3ace..74477ad7467f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }