From patchwork Mon Mar 25 08:34:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161052 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697995jan; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwap1eeuyz4DC9Haxd/y19wrjj2KwZIHfd3SV9HJeKAMjTIOpReB7unmbORfuJ4481Dg5sX X-Received: by 2002:a17:902:aa5:: with SMTP id 34mr23011172plp.302.1553503149160; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503149; cv=none; d=google.com; s=arc-20160816; b=Q6G8qsqiddQQNzD7rii5Twz7XlkoYA7pe9ybECEanXAcCp3L+ffV4t7bKTwkXJ95TL IiY79ePYiu1MJsnBR/6ldm+jPEWA90g0Ce3M12lwDOnTnJaQy5K5Y9dljFJyqtcSU8sU sAXc0VSSh3eJkcdrseBilaDdwDQkKAAaVBsdFTdRZcHxtNzS5soBJk5eeCYnsy8nzbhS 4slcjIi20pWpHaj7YBNzCS8/YvzGmuK43tEy6wGK2CKZJ/jmjvJNsZo4FAsERFy9Iyfn 5V0f3Cae29KDyQiC9BorxDPPThgcPONVxAC/JWNEJMUCCWTfWNYQc0fdCht1E5FNJSXR fifQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; b=NbELVD+2GZH8gUD4CsRLURVE7Ki6OUNoq+OdT8lLtLUYmZvqIy/4vmUOhL0PB4dFMp Q64f9pcFyonwkOrc0kHiFPBqvfgW7DCjDDABNTnjLQ3n6lbZtYI8xYrZMtwkj8DFVXLK 648IIxx/0dcDzkiz8SehC69WHuibrOD8ds84peXqVVZRhPacB6UaG2ysZ0moTjn/ejor 4Dx6URkHdnHFqw5TOsJ/mLuTvf+D6N9rQxHuNXhhZ/YLxxZm8TaQSpNZ4fI5Ra39vPMk h8Ko1QoEmhg824BjGnM3vSlldLKEVkQM/W+ZsULGidBGlln8TbiT+2BIERiOhcNp0RhC fquQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=azTQ0AGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id be11si13340668plb.355.2019.03.25.01.39.08; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=azTQ0AGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730109AbfCYIg3 (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:29 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54822 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729965AbfCYIg1 (ORCPT ); Mon, 25 Mar 2019 04:36:27 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aCpZ106411; Mon, 25 Mar 2019 03:36:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502972; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=azTQ0AGmsp4+BAkPd/6ewSMKH63GZ0o5P4D6DseFRL5X6k7/6OK84uARHwhUGvdM9 GNrFSEWe+s+zEKD3utzivbVQQDYQF/I615Q+dDOmZyWnimnOIqkqyJ2D+1cwVoabV3 3rVetJZ8kBOnVeVUSXpbQiArpNw2S3Y47XQYVbOg= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aBWu091356 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:11 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:11 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFj006534; Mon, 25 Mar 2019 03:36:07 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 25 Mar 2019 14:04:38 +0530 Message-ID: <20190325083501.8088-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1